July 2005

ASM5I9658

rev 0.2

3.3V 1:10 LVCMOS PLL Clock Generator

5 of 14

Notice: The information in this document is subject to change without notice.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input high voltage

2.0

V

LVCMOS

Input low voltage

0.8

V

LVCMOS

Peak-to-peak input voltage

(PCLK)

250

mV

LVPECL

1

Common Mode Range

(PCLK)

1.0

V

LVPECL

Output High Voltage

2.4

V

2

Output Low Voltage

3

0.55

0.30

V

V

Output impedance

14 -17

Ω

Input Current

4

±200

µA

Maximum PLL Supply Current

12

15

mA

Maximum Quiescent Supply Current

13

15

mA

2.The ASM3P9658 is capable of driving 50Ωtransmission lines on the incident edge. Each output drives one 50Ωparallel terminated

3.The ASM5I9658 output levels are compatible to the MPC958 output levels.

4.Inputs have pull-down or pull-up resistors affecting the input current.