July 2005

ASM5I9352

rev 0.2

Alliance Semiconductor

2575, Augustine Drive

• Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer

Features

Output frequency range: 25MHz to 200MHz

Output frequency range: 16.67MHz to 200MHz

Input frequency range: 16.67MHz to 200MHz

2.5V or 3.3V operation

Split 2.5V/3.3V outputs

± 2% max Output duty cycle variation

11 Clock outputs: Drive up to 22 clock lines

LVCMOS reference clock input

125-pS max output-output skew

PLL bypass mode

Spread Aware

TM

Output enable/disable

Pin compatible with MPC9352 and MPC952

Industrial temperature range: –40°C to +85°C

32-Pin 1.0mm TQFP & LQFP Packages

Functional Description

The ASM5I9352 is a low voltage high performance

200MHz PLL-based zero delay buffer designed for high

speed clock distribution applications.

The ASM5I9352 features an LVCMOS reference clock

input and provides 11 outputs partitioned in 3 banks of 5, 4,

and 2 outputs. Bank A divides the VCO output by 4 or 6

while Bank B divides by 4 and 2 and Bank C divides by 2

and 4 per SEL(A:C) settings, see Table 2. These dividers

allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and

1:3. Each LVCMOS compatible output can drive 50Ω series

or parallel terminated transmission lines. For series

terminated transmission lines, each output can drive one or

two traces giving the device an effective fanout of 1:22.

The PLL is ensured stable given that the VCO is configured

to run between 200 MHz to 500 MHz. This allows a wide

range of output frequencies from 16.67 MHz to 200 MHz.

For normal operation, the external feedback input, FB_IN,

is connected to one of the outputs. The internal VCO is

running at multiples of the input reference clock set by the

feedback divider, see Table 1.

When PLL_EN# is HIGH, PLL is bypassed and the

reference clock directly feeds the output dividers. This

mode is fully static and the minimum input clock frequency

specification does not apply.