ASM2I99447 datasheet(5/14 Pages) ALSC

5 / 14 page

May 2005

ASM2I99447

rev 0.3

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

5 of 14

Notice: The information in this document is subject to change without notice.

Table 8. AC Characteristics (V

CC = 2.5V ± 5%, TA = –40°C to +85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency

350

MHz

fmax

Output frequency

350

MHz

fP,REF

Reference Input Pulse Width

1.4

tr, tf

CCLK0, CCLK1 Input Rise/Fall Time

1.0

0.7 to 1.7V

tPLH/HL

Propagation Delay

CCLK0 or CCLK1 to any Q

1.7

4.4

tPLZ, HZ

Output Disable Time

tPZL, ZH

Output Enable Time

Setup Time

CCLK0 or CCLK1 to CLK_STOP

0.0

Hold Time

CCLK0 or CCLK1 to CLK_STOP

1.0

tsk(O)

Output-to-Output Skew

150

tsk(PP)

Device-to-Device Skew

2.7

tSK(P)

DCQ

Output Pulse Skew

Output Duty Cycle

fQ<350 MHz

200

DCREF=50%

tr, tf

Output Rise/Fall Time

0.1

1.0

0.6 to 1.8V

tJIT(CC)

Cycle-to-cycle jitter

RMS (1

σ)

TBD

Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT.

2. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse

width, output duty cycle and maximum frequency specifications.

3. Setup and hold times are referenced to the falling edge of the selected clock signal input.

4. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.

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