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AS7C34096A bảng dữ liệu(PDF) 5 Page - Alliance Semiconductor Corporation

tên linh kiện AS7C34096A
Giải thích chi tiết về linh kiện  3.3V 512K x 8 CMOS SRAM
PDF  9 Pages
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nhà sản xuất  ALSC [Alliance Semiconductor Corporation]
Trang chủ  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C34096A bảng dữ liệu(HTML) 5 Page - Alliance Semiconductor Corporation

  AS7C34096A Datasheet HTML 1Page - Alliance Semiconductor Corporation AS7C34096A Datasheet HTML 2Page - Alliance Semiconductor Corporation AS7C34096A Datasheet HTML 3Page - Alliance Semiconductor Corporation AS7C34096A Datasheet HTML 4Page - Alliance Semiconductor Corporation AS7C34096A Datasheet HTML 5Page - Alliance Semiconductor Corporation AS7C34096A Datasheet HTML 6Page - Alliance Semiconductor Corporation AS7C34096A Datasheet HTML 7Page - Alliance Semiconductor Corporation AS7C34096A Datasheet HTML 8Page - Alliance Semiconductor Corporation AS7C34096A Datasheet HTML 9Page - Alliance Semiconductor Corporation  
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®
AS7C34096A
8/17/04, v. 2.1
Alliance Semiconductor
P. 5 of 9
Write waveform 1 (WE controlled)10
Write cycle (over the operating range)10
Parameter
Symbol
–10
–12
–15
–20
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Write cycle time
tWC
10–12–
15–20–
ns
Chip enable (CE) to write end
tCW
7
–
8
–
10–12–
ns
Address setup to write end
tAW
7
–
8
–
10–12–
ns
Address setup time
tAS
0–0
–0–
0–
ns
Write pulse width (OE = high)
tWP1
7
–
8
–
10–12–
ns
Write pulse width (OE = low
tWP2
10–12–
15–20–
ns
Address hold from end of write
tAH
0–0
–0–
0–
ns
Write recovery time
tWR
0–0
–0–
0–
ns
Data valid to write end
tDW
5–6
–7–
9–
ns
Data hold time
tDH
0–0
–0–
0–
ns
4, 5
Write enable to output in high Z
tWZ
050
607
09
ns
4, 5
Output active from write end
tOW
3–3
–3–
3–
ns
4, 5
tAW
tAH
tWC
Address
WE
DOUT
tDH
tOW
tDW
tWZ
tWP
tAS
Data valid
DIN
tWR



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