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FIDO5210BBCZ bảng dữ liệu(PDF) 3 Page - Analog Devices |
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FIDO5210BBCZ bảng dữ liệu(HTML) 3 Page - Analog Devices |
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3 / 19 page ![]() Data Sheet fido5100/fido5200 Rev. E | Page 3 of 19 SPECIFICATIONS REM SWITCH CHARACTERISTICS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments OPERATING CONDITIONS Core Voltage 1.08 1.2 1.32 V Core Current 48 mA At TA = 85°C Input/Output (I/O) Buffers 2.97 3.3 3.63 V 3.3 V power supply I/O Current 0.035 mA At TA = 85°C PLL Analog Voltage Regulator Power Supply 1.08 1.2 1.32 V DC Input Voltage −0.5 +3.8 V Output Voltage −0.5 +3.8 V Operating Junction Temperature (Industrial) −40 +125 °C DC CHARACTERISTICS (I/O STANDARD) 3.3 V LVCMOS VCC+3V3 2.97 3.3 3.63 V Voltage level applied to the VCC+3V3 signal Input Voltage Low (VIL) −0.3 +0.8 V High (VIH) 2.0 3.6 V Output Voltage Low (VOL) 0.4 V High (VOH) 2.4 V Output Current Low (IOL) 8.2 13.0 16.1 mA High (IOH) 9.2 19.2 30.7 mA LEAKAGE CURRENT Input Pin −10 +10 μA Input voltage (VIN) = 0 V to 3.3 V maximum Tristated I/O Pin −10 +10 μA Output voltage (VOUT) = 0 V to 3.3 V maximum HOST INTERFACE TRANSFER RATE1 32 Bits Per 28 ns 1 Supports EtherCAT cycle times down to 12.5 μs and PROFINET cycle times down to 31.25 μs. TIMING SPECIFICATIONS—NONMULTIPLEXED ADDRESS DATA BUS Table 2. Nonmultiplexed Address Data Bus—Read and Write Cycle Timing1, 2, 3 Parameter Min Typ Max Unit Description tAS 2 ps Address setup time tAH 370 ps Address hold time tCDV 20 ns CS to data valid time tODV 20 ns Output enable to data valid time tOEL 20 ns Output enable low time tCSH 8 ns CS high time tCSL 20 ns CS low time tEOE 0 ns CS to output enable time tCOE 0 ns Output enable high to CS high tDO 150 ps Output enable to data drive time tDHZ 110 ps Output disable to high-Z time tCHZ 110 ps CS high to high-Z time tWES 0 ns CS to write enable tWEWC 16 ns Write enable to write complete tWECS 0 ns Write enable high to CS high tDS 30 ps Data setup to WE high tDH 30 ps Input data hold after WE high 1 The MBS pin determines whether the host interfaced has multiplexed or separate address and data lines. When MBS = 0, the interface is nonmultiplexed. 2 OE can be taken low before CS. Therefore, tEOE can be a negative value. In this case, a board designer must closely monitor tDO and tCDV to avoid bus contention and ensure proper data transfer. 3 The read bus cycle terminates when either CS or OE is taken high. Therefore, a negative value for tCOE is acceptable in some circumstances. |
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