SN74HCS264 8-Bit Parallel-Out Serial Shift Registers With Schmitt-Trigger Inputs and

Inverted Outputs

1 Features

• Wide operating voltage range: 2 V to 6 V

• Schmitt-trigger inputs allow for slow or noisy input

signals

• Low power consumption

– Typical input leakage current of ±100 nA

• ±7.8-mA output drive at 6 V

• Extended ambient temperature range: –40°C to

2 Applications

• Output expansion

• LED matrix control

• 7-segment display control

• 8-bit data storage

3 Description

The SN74HCS264 device contains an 8-bit shift

register with AND-gated serial inputs and an

asynchronous clear (CLR) input. Data at the serial

inputs can be changed while CLK is high or low,

provided the minimum setup time requirements are

met. All inputs include Schmitt-trigger architecture,

adding noise margin and eliminating any input

transition rate requirement. Clocking occurs on the

low-to-high-level transition of CLK.

Upon a clock trigger, the device will store the result of

the (A ● B) input data line in the first register and

propagate each register’s data to the next register.

The outputs are inverted from the data stored.

Device Information

PART NUMBER

PACKAGE(1)

BODY SIZE (NOM)

SN74HCS264PW

TSSOP (16)

5.00 mm × 4.40 mm

SN74HCS264D

SOIC (16)

9.90 mm × 3.90 mm

(1)

For all available packages, see the orderable addendum at

the end of the data sheet.

Input Voltage

Schmitt-trigger

CMOS Input

Response

Waveforms

Standard

CMOS Input

Response

Waveforms

Input Voltage

Input Voltage

Time

Time

Input Voltage

Waveforms

Low Power

Noise Rejection

Supports Slow Inputs

Time

Time

Time

Time

Benefits of Schmitt-trigger inputs

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SN74HCS264

SCLS844 – AUGUST 2020

Copyright © 2020 Texas Instruments Incorporated

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SN74HCS264

SCLS844 – AUGUST 2020

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.