AWR2243_V01 datasheet(39/62 Pages) TI

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9.3.2 Host Interface

The AWR2243 device communicates with the host radar processor over the following main interfaces:

• Reference Clock – Reference clock available for host processor after device wakeup

• Control – 4-port standard SPI (slave or I2C) for host control along with HOST INTR pin for async events.. All

radio control commands (and response) flow through this interface.

• Data – High-speed serial port following the MIPI CSI2 format. Four data and one clock lane (all differential).

Data from different receive channels can be multiplexed on a single data lane to optimize board routing. This

is a unidirectional interface used for data transfer only.

• Reset – Active-low reset for device wakeup from host

• Out-of-band interrupt

• Error – Used for notifying the host in case the radio controller detects a fault

9.4 Other Subsystems

9.4.1 A2D Data Format Over CSI2 Interface

The AWR2243 device uses MIPI D-PHY / CSI2-based format to transfer the raw A2D samples to the external

MCU. This is shown in Figure 9-4.

• Supports four data lanes

• CSI-2 data rate scalable from 150 Mbps to 600 Mbps per lane

• Virtual channel based

• CRC generation

Frame Period

Acquisition Period

Frame

Ramp/Chirp

Data Ready

ST SP ET

Short

Packet

LPS

ST SP ET

Short

Packet

LPS

Chirp 1 data

Data rate/Lane should be such that "Chirp + Interchirp" period

should be able to accommodate the data transfer

ST SP ET

Short

Packet

Normal Mode

DATA

Long

Packet

LPS

.5 s-.8 s

Frame Start – CSi2 VSYNC Start Short Packet

Line Start – CSI2 HSYNC Start Short Packet

Line End – CSI2 HSYNC End Short Packet

Frame End – CSi2 VSYNC End Short Packet

Figure 9-4. CSI-2 Transmission Format

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AWR2243

SWRS223A – FEBRUARY 2020 – REVISED AUGUST 2020

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