JS28F256P30T85 datasheet(96/102 Pages) INTEL

96 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

C.4

Device Geometry Definition

Table 36.

Device Geometry Definition

Offset

Length

Description

Code

27h

“n” such that device size = 2

n in number of bytes

27:

See table below

28h

—

x64

x32

x16

28:

--01

x16

——

———

——

—

29:

--00

2Ah

“n” such that maximum number of bytes in write buffer = 2

2A:

--06

2B:

--00

2Ch

2C:

2Dh

Erase Block Region 1 Information

2D:

bits 0–15 = y, y+1 = number of identical-size erase blocks

2E:

bits 16–31 = z, region erase block(s) size are z x 256 bytes

2F:

30:

31h

Erase Block Region 2 Information

31:

bits 0–15 = y, y+1 = number of identical-size erase blocks

32:

bits 16–31 = z, region erase block(s) size are z x 256 bytes

33:

34:

35h

Reserved for future erase block region information

35:

36:

37:

38:

See table below

Flash device interface code assignment:

"n" such that n+1 specifies the bit field that represents the flash

device width capabilities as described in the table:

Number of erase block regions (x) within device:

1. x = 0 means no erase blocking; the device erases in bulk

2. x specifies the number of device regions with one or

more contiguous same-size erase blocks.

3. Symmetrically blocked partitions have one blocking region

A ddress

64-Mbit

–B

–T

–B

–T

–B

–T

27:

--17

--18

--19

28:

--01

29:

--00

2A :

--06

2B:

--00

2C:

--02

2D:

--03

--3E

--03

--7E

--03

--FE

2E:

--00

2F:

--80

--00

--80

--00

--80

--00

30:

--00

--02

--00

--02

--00

--02

31:

--3E

--03

--7E

--03

--FE

--03

32:

--00

33:

--00

--80

--00

--80

--00

--80

34:

--02

--00

--02

--00

--02

--00

35:

--00

36:

--00

37:

--00

38:

--00

128-Mbit

256-Mbit

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