IS25LP032D-RGLA3:P datasheet(3/118 Pages) ISSI

3 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

GENERAL DESCRIPTION

The IS25LP032D and IS25WP032D Serial Flash memory offers a versatile storage solution with high flexibility and

performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems that

require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire SPI

Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable

(CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).

The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies

of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66Mbytes/s of

data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer

addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash

memories allowing for efficient memory access to support XIP (execute in place) operation.

Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory.

QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be

erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector

and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of

applications requiring solid data retention.

GLOSSARY

Standard SPI

In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),

Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,

addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the

status of the device. This device supports SPI bus operation modes (0, 0) and (1, 1).

Multi I/O SPI

Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input

and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode

will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.

QPI

The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from

Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol requires

that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The QPI mode

utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can significantly

reduce the SPI instruction overhead and improve system performance. Only QPI mode or SPI/Dual/Quad mode

can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used to switch between these

two modes, regardless of the non-volatible Quad Enable (QE) bit status in the Status Register. Power Reset or

Software Reset will return the device into the standard SPI mode. SI and SO pins become bidirectional I/O0 and

I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively during QPI mode.

DTR

In addition to SPI and QPI features, the device also supports Fast READ DTR operation. Fast READ DTR operation

allows high data throughput while running at lower clock frequencies. Fast READ DTR operation uses both rising

and falling edges of the clock for address inputs, and data outputs, resulting in reducing input and output cycles by

half.

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