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IS25LP064A-RBLE1 bảng dữ liệu(PDF) 67 Page - Integrated Silicon Solution, Inc

tên linh kiện IS25LP064A-RBLE1
Giải thích chi tiết về linh kiện  3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  99 Pages
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nhà sản xuất  ISSI [Integrated Silicon Solution, Inc]
Trang chủ  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP064A-RBLE1 bảng dữ liệu(HTML) 67 Page - Integrated Silicon Solution, Inc

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IS25LP064A/032A
Integrated Silicon Solution, Inc.- www.issi.com
67
Rev. A
11/06/2015
8.33 INFORMATION ROW ERASE OPERATION (IRER, 64h)
Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to the
operation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is
automatically reset after the completion of the operation.
The sequence of IRER operation: Pull CE# low to select the device  Send IRER instruction code  Send
three address bytes  Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE#
is pulled high, Erase operation will begin immediately. The internal control logic automatically handles the erase
voltage and timing. Refer to Figure 8.49 for IRER Sequence.
Figure 8.52 IRER (Information Row Erase) Sequence
Instruction = 64h
23
CE #
SCK
SI
3
2
SO
1
0
3-byte Address
High Impedance
22
21
...
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
Mode 3
Mode 0



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