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IS25LP032D-RKLE:P bảng dữ liệu(PDF) 36 Page - Integrated Silicon Solution, Inc

tên linh kiện IS25LP032D-RKLE:P
Giải thích chi tiết về linh kiện  SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  118 Pages
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nhà sản xuất  ISSI [Integrated Silicon Solution, Inc]
Trang chủ  http://www.issi.com
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IS25LP032D-RKLE:P bảng dữ liệu(HTML) 36 Page - Integrated Silicon Solution, Inc

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IS25LP032D
IS25WP032D
Integrated Silicon Solution, Inc.- www.issi.com
36
Rev. A12
08/04/2020
8.2 FAST READ OPERATION (FRD, 0Bh)
The FAST READ (FRD) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ instruction code is followed by three address bytes (A23 - A0) and dummy cycles (configurable,
default is 8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first
data byte from the address is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT,
during the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST READ
instruction is terminated by driving CE# high (VIH).
If the FAST READ instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction
is ignored without affecting the current cycle.
Figure 8.2 Fast Read Sequence
Instruction = 0Bh
3-byte Address
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
...
7
6
CE #
SCK
SI
5
3
2
SO
4
1
Data Out
23
CE #
SCK
SI
3
2
SO
1
0
High Impedance
22
21
...
0
1
2
3
4
5
6
7
8
9
10
...
Mode 3
Mode 0
tV
Dummy Cycles
0
...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.



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