T1024 datasheet(18/49 Pages) FREESCALE

tên linh kiện	T1024

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T1024

XFI

EMI2

AQR105

10G Base-T

PHY

MDI

Magnetics

RJ46

Figure 2-6. XFI interface

2.7.3 SGMII support

The T1024 processor supports evaluation of the 2.5G SGMII protocol for serialized

Ethernet PHYs using Aquantia AQR105 PHY. Ethernet data is carried over the SGMII

interface.

The below figure shows the connectivity of the SGMII interface.

SGMII

T1024

EMI2

Transformer

MDIO/MDC

RJ-46 Port

AQR105

Figure 2-7. SGMII interface

2.8 Ethernet controllers

The T1024 processor supports two Ethernet Controllers (EC), which can connect to

Ethernet PHYs using MII or RGMII protocols. On the T1024RDB, the EC1 and EC2

ports only operate in the RGMII mode. Both ports are connected to Realtek RTL8211

PHYs. The T1024RDB supports Energy Efficient Ethernet (EEE) on EC1 and sleep

mode on EC2.

The below figure shows the connectivity of the EC1/EC2 interface.

Ethernet controllers

QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015

Freescale Semiconductor, Inc.

T1024 bảng dữ liệu(PDF) 18 Page - Freescale Semiconductor, Inc