LP4067-01

Dec.-2019

www.lowpowersemi.com

Page 2 of 8

Preliminary Datasheet

LP4067

Functional Pin Description

Package Type

Pin Configurations

LP4067AB6F

LP4067TB6F

SOT23-6

5

1

3

6

4

EN

2

GND

CHRG

ISET

BAT

VIN

5

1

3

6

4

TS

2

GND

VIN

ISET

CHRG

BAT

Pin Description

NAME

No.

DESCRIPTION

LP4067A

LP4067T

EN

1

Charge Enable Input (active low).

TS

1

Temperature senses voltage input.

GND

2

2

GND is the connection to system ground.

CHRG

3

5

Open-Drain Charge Status Output. When the battery is charging, the CHRG

pin is pulled low by an internal NMOS. When the charge cycle is completed,

the pin could be pulled High by an external pull high resistor.

VIN

4

3

VIN is the input power source. Connect to a wall adapter.

BAT

5

4

BAT is the connection to the battery. Typically a 10µF Tantalum capacitor is

needed for stability when there is no battery attached. When a battery is

attached, only a 1uF ceramic capacitor is required.

ISET

6

6

Charge Current Program. The charge current is programmed by connecting a

1% resistor(RISET) to ground.