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SAMV71Q21 bảng dữ liệu(PDF) 26 Page - Microchip Technology

tên linh kiện SAMV71Q21
Giải thích chi tiết về linh kiện  SAM E70/S70/V70/V71 Family Silicon Errata and Data Sheet Clarification
PDF  41 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
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13.
Quad Serial Peripheral Interface (QSPI)
13.1
Module Hangs with Long DLYCS
The QSPI module hangs if a command is written to any QSPI register during the delay defined in the
DLYCS bit. There is no status bit to flag the end of the delay.
Workaround
The DLYCS bit defines a minimum period over which the Chip Select is deasserted, which is required by
some memories. This delay is generally less than 60 ns and comprises internal execution time,
arbitration, and latencies. Therefore, the DLYCS bit must be configured to be slightly higher than the
value specified for the slave device. The software must wait for at least this same period of time before a
command can be written to the QSPI module.
Affected Silicon Revisions
A
B
X
X
13.2
WDRBT
When the QSPI is configured in SPI mode, the Wait Data Read Before Transfer (WDRBT) feature does
not work.
Workaround
None.
Affected Silicon Revisions
A
B
X
X
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
© 2018 Microchip Technology Inc.
Datasheet Errata
DS80000767C-page 26



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