DS60001484 datasheet(21/46 Pages) MICROCHIP

21 / 46 page

Tip: In case of non-use at application level of the QSPI embedded in SAMA5D27 SOM1, it is

possible to reassign the signals dedicated to QSPI memory to another PIO function as defined

in the table below. To do so, the DIS_BOOT pin (SAMA5D27 SOM1 pad 126) must be forced to

ground.

Table 5-3. Other GPIO Possibilities for QSPI Interface in Case of Non-use

Pin Number Power Rail

Primary

PIO Peripheral

Reset State

Signal

Dir

Func

Signal

Dir

IOset

134

VDDIN_3V3

PB05

I/O

TCLK2

PIO, I, PU,

PWMH2

QSPI1_SCK

127

VDDIN_3V3

PB06

I/O

TIOA2

I/O

PIO, I, PU,

PWML2

QSPI1_CS

133

VDDIN_3V3

PB07

I/O

TIOB2

I/O

PIO, I, PU,

PWMH3

QSPI1_IO0

I/O

128

VDDIN_3V3

PB08

I/O

TCLK3

PIO, I, PU,

PWML3

QSPI1_IO1

I/O

132

VDDIN_3V3

PB09

I/O

TIOA3

I/O

PIO, I, PU,

PWMFI1

QSPI1_IO2

I/O

135

VDDIN_3V3

PB10

I/O

TIOB3

I/O

PIO, I, PU,

PWMEXTRG1

QSPI1_IO3

I/O

Tip: The QSPI interface can be shared with another external device. To do so, the QSPI_CS#

node must stay at "High" level. That means that the DIS_BOOT pin (SAMA5D27 SOM1 pad

126) must be forced to ground.

5.6

EEPROM Memory

The SAMA5D27 SOM1 embeds the 24AA02E48T-I/OT, a 1Kb Serial EEPROM with pre-programmed

EUI-48 MAC address.

The device is organized as one block of 128 x 8-bit memory with a 2-wire serial interface. The second

block is reserved for MAC Address storage.

SAMA5D27 SOM1

Datasheet

DS60001521A-page 21

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