H5GQ2H24AFR-R0C datasheet(128/172 Pages) HYNIX

tên linh kiện	H5GQ2H24AFR-R0C

Giải thích chi tiết về linh kiện	2Gb (64Mx32) GDDR5 SGRAM

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128 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

128

H5GQ2H24AFR

2. AC noise in the system is estimated at 50mV pk‐pk for the purpose of DRAM design.

3. Source of Reference Voltage and control of Reference Voltage for DQ and DBI# pins is determined by VREFD, Half VREFD, Auto

VREFD, VREFD MERGE and VREFD Offsets mode registers.

4. VREFD Offsets are not supported with VREFD2.

5. External VREFC is to be provided by the controller as there is no other alternative supply.

6. DQ/DBI# input slew rate must be greater than or equal to 3V/ns for POD15 and 2.7V/ns for POD135 . The slew rate is measured

between VREFD crossing and VIHD(AC) or VILD(AC) or VREFD2 crossing and VIHD2(AC) or VILD2(AC).

7. ADR/CMD input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and

VIHA(AC) or VILA(AC).

8. VIHX and VILX define the voltage levels for the receiver that detects x32 or x16 mode with RESET# going High.

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