H5GQ2H24AFR-R0C datasheet(113/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

113

H5GQ2H24AFR

1. Minimum CKE# pulse width must satisfy tCKE.

2. After issuing Power‐Down command, two more NOPs should be issued.

5.18. COMMAND TRUTH TABLES

Notes:

1. CKE#n is the logic state of CKE# at clock edge n; CKE#n‐1 was the state of CKE# at the previous clock edge.

2. Current state is the state of the GDDR5 SGRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSRW period. A minimum of tLK is

needed for the PLL to lock before applying a READ or WRITE command if the PLL was disabled.

Table 28 Pin States During Power Down

LP2

State

EDC

WCK

‘Hold’

no WCK

High

DQ/DBI#

ODT

ADR/CMD

ODT

CKE#

ODT (Driven High by Controller)

WCK/WCK#

ODT

Table 29 Truth Table – CKE#

CKE#n‐1

CKE#n

CURRENT

STATE

COMMANDn

ACTIONn

NOTES

Power‐Down

Maintain Power‐Down

Self Refresh

Maintain Self Refresh

Power‐Down

DESELECT or NOP

Exit Power‐Down

Self Refresh

DESELECT or NOP

Exit Self Refresh

All Banks Idle

DESELECT or NOP

Precharge Power‐Down Entry

Bank(s) Active

DESELECT or NOP

Active Power‐Down Entry

All Banks Idle

REFRESH

Self Refresh Entry

See <Link>Table 30 and

<Link>Table 31

1, 2, 3

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