7

01.10.05 REV 6

All data sheets are subject to change without notice

©2005 Maxwell Technologies

All rights reserved.

14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC

9240LP

LOGIC OUTPUTS (with DRVDD = 5V)

High Level Output Voltage (I

High Level Output Voltage (I

Low Level Output Voltage (I

Low Level Output Voltage (I

Output Capacitance

1, 2, 3

V

OH

V

OH

V

OL

V

OL

C

OUT

5

4.5

2.4

0.4

0.1

--

V min

V min

V max

V max

pF typ

1. Due to the voltage drop across the LPT circuiry the CLOCK signal must be no greater than AVDD - 0.5V

2. Guaranteed by design

(T

1. Guaranteed by design

Clock Period

CLOCK Pulse width High

CLOCK Pulse width Low

Output Delay

Pipeline Delay (Latency)

t

C

t

CH

t

CL

t

OD

100

45

45

8

--

--

--

--

13

--

--

--

--

19

--3

ns

ns

ns

ns

Clock Cycles

(AVDD = 5V, DVDD = 5V, T