8143 datasheet(13/24 Pages) MAXWELL

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12-Bit Serial Daisy-Chain D/A Converter

8143

07.23.03 REV 3

FIGURE 14. SIMPLIFIED CIRCUIT

Where R

O is a function of the digital code, and:

O = 10 kΩ for more than four bits of Logic 1,

O = 30 kΩ for any single bit of Logic 1.

Therefore, the offset gain varies as follows:

at code 0011 1111 1111,

at code 0100 0000 0000,

The error difference is 2/3 V

OS.

Since one LSB has a weight (for V

REF = 10V) of 2.4 mV for the 8143, it is clearly important that VOS be minimized,

using either the amplifier’s pulling pins, an external pulling network, or by selection of an amplifier with inherently low

OS. Amplifiers with sufficiently low VOS include OP77, OP07 and OP27.

Interface Logic Operation

The microprocessor interface of the 8143 has been designed with multiple STROBE and LOAD inputs to maximize

interfacing options. Control signals decoding may be done on chip or with the use of external decoding circuitry (see

Figure 21).

Serial data is clocked into the input register and buffered output stage with STB

1, STB2, or STB4. The strobe inputs are

active on the rising edge. STB

3 may be used with a falling edge clock data.

Serial data output (SRO) follows the serial data input (SRI) by 12 clocked bits.

Holding any STROBE input at its selected state (i.e., STB

1, STB2, or STB4 at logic HIGH or STB3 at logic LOW) will act

to prevent any further data input.

When a new data word has been entered into the input register, it is transferred to the DAC register by asserting both

LOAD inputs.

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