M41T00S datasheet(12/23 Pages) STMICROELECTRONICS

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M41T00S

12/23

Calibrating the Clock

The M41T00S is driven by a quartz-controlled os-

cillator with a nominal frequency of 32,768 Hz. The

devices are tested not exceed ±35 ppm (parts per

million) oscillator frequency error at 25oC, which

equates to about ±1.53 minutes per month (see

Figure 11., page 13). When the Calibration circuit

is properly employed, accuracy improves to better

than ±2 ppm at 25°C.

The oscillation rate of crystals changes with tem-

perature. The M41T00S design employs periodic

counter correction. The calibration circuit adds or

subtracts counts from the oscillator divider circuit

at the divide by 256 stage, as shown in Figure

12., page 13. The number of times pulses which

are blanked (subtracted, negative calibration) or

split (added, positive calibration) depends upon

the value loaded into the five Calibration Bits found

in the Calibration Register. Adding counts speeds

the clock up, subtracting counts slows the clock

down.

The Calibration Bits occupy the five lower order

bits (D4-D0) in the Calibration Register 07h. These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 minutes in the cycle may, once

per minute, have one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minutes in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step in the calibration register (see Figure

12., page 13). Assuming that the oscillator is run-

ning at exactly 32,768 Hz, each of the 31 incre-

ments in the Calibration byte would represent

+10.7 or –5.35 seconds per month which corre-

sponds to a total range of +5.5 or –2.75 minutes

per month.

Two methods are available for ascertaining how

much calibration a given M41T00S may require.

The first involves setting the clock, letting it run for

a month and comparing it to a known accurate ref-

erence and recording deviation over a fixed period

of time. Calibration values, including the number of

seconds lost or gained in a given period, can be

found in Application Note AN934, “TIMEKEEP-

ER® CALIBRATION.” This allows the designer to

give the end user the ability to calibrate the clock

as the environment requires, even if the final prod-

uct is packaged in a non-user serviceable enclo-

sure. The designer could provide a simple utility

that accesses the Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

FT/OUT pin. The pin will toggle at 512Hz, when

the Stop Bit (ST, D7 of 00h) is '0,' and the Frequen-

cy Test Bit (FT, D6 of 07h) is '1.'

Any deviation from 512 Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature.

For

example,

reading

512.010124 Hz would indicate a +20 ppm oscilla-

tor frequency error, requiring a –10 (XX001010) to

be loaded into the Calibration Byte for correction.

Note that setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency.

The FT/OUT pin is an open drain output which re-

quires a pull-up resistor to VCC for proper opera-

tion. A 500-10k resistor is recommended in order

to control the rise time. The FT Bit is cleared on

power-down.

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