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ADAV801ASTZ bảng dữ liệu(PDF) 6 Page - Analog Devices

tên linh kiện ADAV801ASTZ
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nhà sản xuất  AD [Analog Devices]
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ADAV801ASTZ bảng dữ liệu(HTML) 6 Page - Analog Devices

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ADAV801
Rev. 0 | Page 6 of 56
Parameter
Min
Typ
Max
Unit
Comments
Operating Current
All supplies at 3.3 V
Analog Current
60
mA
Digital Current
38
mA
Digital Interface Current
13
mA
DIRIN/DIROUT Current
5
mA
PLL Current
18
mA
Power-Down Current
RESET low, no MCLK
Analog Current
18
mA
Digital Current
2.5
mA
Digital Interface Current
700
µA
DIRIN/DIROUT Current
3.5
mA
PLL Current
900
µA
Power Supply Rejection
Signal at Analog Supply Pins
−70
dB
1 kHz, 300 mV p-p
−70
dB
20 kHz, 300 mV p-p
1 Guaranteed by design.
TIMING SPECIFICATIONS
Timing specifications are guaranteed over the full temperature and supply range.
Table 3.
Parameter
Min
Typ
Max
Unit
Comments
MASTER CLOCK AND RESET
fMCLK
MCLKI Frequency
12.288
54
MHz
fXIN
XIN Frequency
27.0
54
MHz
tRESET
RESET Low
20
ns
SPI PORT
tCCH
CCLK High
40
ns
tCCL
CCLK Low
40
ns
tCIS
CIN Setup
10
ns
To CCLK rising edge
tCIH
CIN Hold
10
ns
From CCLK rising edge
tCLS
CLATCH Setup
10
ns
To CCLK rising edge
tCLH
CLATCH Hold
10
ns
From CCLK rising edge
tCOE
COUT Enable
15
ns
From CLATCH falling edge
tCOD
COUT Delay
20
ns
From CCLK falling edge
tCOTS
COUT Three-State
25
ns
From CLATCH rising edge
SERIAL PORTS1
Slave Mode
tSBH
xBCLK High
40
ns
tSBL
xBCLK Low
40
ns
fSBF
xBCLK Frequency
64 × fS
tSLS
xLRCLK Setup
10
ns
To xBCLK rising edge
tSLH
xLRCLK Hold
10
ns
From xBCLK rising edge
tSDS
xSDATA Setup
10
ns
To xBCLK rising edge
tSDH
xSDATA Hold
10
ns
From xBCLK rising edge
tSDD
xSDATA Delay
10
ns
From xBCLK falling edge



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