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IMX8DXIEC bảng dữ liệu(HTML) 28 Page - NXP Semiconductors |
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28 / 127 page  Electrical characteristics i.MX 8DualX Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 28 4.3 PLL electrical characteristics 4.3.1 PLLs of subsystems i.MX 8DualX embeds a large number of PLLs to address clocking requirements of the various subsystems. These PLLs are controlled through the SCU and not directly by Cortex-A or Cortex-M4F processors. A software API shall be used by those processors to access the PLL settings. Additional PLLs are specific to high-performance interfaces. These are described in the following sections. This table summarizes the PLLs controlled by the SCU. Table 14. PLLs controlled by SCU Subsystem PLL usage Source clock Locking range1 Lock freq. Unit Min freq. Max freq. Cortex-A35 Subsystem 24 650 1300 • Overdrive: 1200 • Nominal: 9002 GPU PLL #0: subsystem 24 648 1344 • Nominal: 7443 MHz PLL #1: shaders 24 648 1344 • Nominal: 7443 MHz DRC (DRAM Controller) Subsystem 24 1250 2500 • LPDDR4: 2400 • DDR3L: 18664 MHz DB (DRAM Block) Subsystem 24 650 1300 1200 MHz Display Controller 0 PLL #0: subsystem 24 650 1300 800 MHz PLL #1: display clock #0 24 650 1300 User-configurable MHz PLL #2: display clock #1 24 650 1300 User-configurable MHz Imaging Subsystem 24 650 1300 1200 MHz ADMA5 PLL #0: subsystem 24 650 1300 1280 MHz PLL #1: audio PLL #0 24 650 1300 User-configurable MHz PLL #2: audio PLL #1 24 650 1300 User-configurable MHz PLL #3: Parallel LCD display 24 650 1300 Pixel freq. ×N MHz Connectivity PLL #0: Subsystem 24 650 1300 792 MHz PLL #1: PHY 24 650 1300 1000 MHz HSIO (High-speed I/O) Subsystem 24 650 1300 800 MHz LSIO (Low-speed I/O) Subsystem 24 650 1300 800 MHz Cortex-M4 Subsystem 24 650 1300 792 MHz VPU PLL #0: subsystem 24 650 1300 1200 MHz |
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