AM29LV800D datasheet(45/51 Pages) AMD

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Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

PR EL IM IN A R Y

Erase and Programming Performance

Notes:

1. Typical program and erase times assume the following conditions: 25

°C, 3.0 V VCC, 1,000,000 cycles.

Additionally, programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most

bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See Table 5 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

Latchup Characteristics

Includes all pins except VCC. Test conditions: VCC =

3.0 V, one pin at a time.

TSOP and SO Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

Data Retention

Parameter

Typ (Note

Max (Note 2)

Unit

Comments

Sector Erase Time

Excludes 00h programming

prior to erasure

Chip Erase Time

Byte Programming Time

300

µs

Excludes system level

overhead (Note 5)

Word Programming Time

360

µs

Chip Programming

Time

(Note 3)

Byte Mode

8.4

Word Mode

5.8

Description

Min

Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to VSS on all I/O pins

–1.0 V

VCC + 1.0 V

VCC Current

–100 mA

+100 mA

Parameter

Symbol

Parameter Description

Test Setup

Typ

Max

Unit

CIN

Input Capacitance

VIN = 0

7.5

COUT

Output Capacitance

VOUT = 0

8.5

CIN2

Control Pin Capacitance

VIN = 0

7.5

Parameter

Test

Conditions

Min

Unit

Minimum Pattern Data Retention Time

150°C

Years

125°C

Years

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