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2ED2184S06F bảng dữ liệu(PDF) 15 Page - Infineon Technologies AG |
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2ED2184S06F bảng dữ liệu(HTML) 15 Page - Infineon Technologies AG |
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15 / 24 page ![]() Datasheet 15 of 24 V 2.21 www.infineon.com/soi 2020-07-07 2ED2181 (4) S06F (J) 650 V high-side and low-side driver with integrated bootstrap diode A) B) C) D) Figure 16 A) Q1 conducting B) D2 conducting C) D3 conducting D) Q4 conducting The circuit shown in Figure 17-A depicts one leg of the three phase inverter; Figures 17-B and 17-C show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin). A B C Figure 17 Figure A shows the Parasitic Elements. Figure B shows the generation of VS positive. Figure C shows the generation of VS negative 5.10 NTSOA – Negative Transient Safe Operating Area In a typical motor drive system, dV/dt is typically designed to be in the range of 3 – 5 V / ns. The negative VS transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An indication of the 2ED2181’s robustness can be seen in Figure 18, where the 2ED2181’s Safe Operating Area is shown at VBS=15 V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside the SOA. |
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