AMC7823 datasheet(39/48 Pages) TI

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DAC Configuration Register (Read/Write)

Load DAC Register (Read/Write)

AMC7823

SLAS453A – APRIL 2005 – REVISED OCTOBER 2005

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

LSB

SLDA7

SLDA6

SLDA5

SLDA4

SLDA3

SLDA2

SLDA1

SLDA0

GDAC7

GDAC6

GDAC5

GDAC4

GDAC3

GDAC2

GDAC1

GDAC0

SLDA-n

DAC Synchronous Load Enable bit.

SLDA-n = 1: Synchronous Load enabled. When the synchronous load DAC signal occurs, DAC-n

Latch is loaded with the value of the corresponding DAC-n Data Register, and the output of

DAC-n is updated immediately. This load signal can be the rising edge of the external signal

ELDAC or the internal load signal ILDAC. Writing the data word 0xBB00 into the LOAD DAC

only, and does not change the DAC-n output.

SLDA-n = 0: Asynchronous Load enabled. A write command to the DAC-n Data Register

immediately updates DAC-n Latch and the output of DAC-n. The synchronous load DAC signal

(ILDAC or ELDAC) does not affect DAC-n.

GDAC-n

DAC-n Output Buffer Amplifier Gain bit.

GDAC-n = 1: The gain of the DAC-n output buffer amplifier is equal to 2.

GDAC-n = 0: The gain of the DAC-n output buffer amplifier is equal to 1.

The combination of the bit GDAC-n and the reference voltage (internal or external) sets the full-scale range of

each DAC-n.

Table 11 describes the full-scale DAC output range as a function of bits SREF, GREF and GDAC-n.

Table 11. Full-Scale DAC Output Range

OUTPUT RANGE

SREF

GREF

GDAC-n

REFERENCE

AVDD = 3 V

AVDD = 5 V

Internal 1.25 V

0 V to 1.25 V

Internal 1.25 V

0 V to 2.50 V

Internal 2.5 V

0 V to 2.50 V

Internal 2.5 V

Saturated at 3 V

0 V to 5.00 V

Don't

0 V to External VREF,

External VREF

care

External VREF ≤ AVDD

Don't

0 V to External VREF × 2

External VREF

care

× External V

REF ≤ AVDD

× External V

REF ≤ AVDD

When an external reference is applied, the full-scale output range of DAC-n is equal to VREF for GDAC = 0, and

equal to 2 x VREF for GDAC-n = 1.

To avoid saturation, the full-scale output range of DAC-n must not be greater than AVDD. After power-on or reset,

all bits are cleared to '0'.

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

LSB

The data word 0xBB00 (shown above) written into the LOAD DAC Register generates ILDAC, the internal load

DAC signal. ILDAC and the external ELDAC signal work in a similar manner. ILDAC shifts data from the DAC-n

Data register to the DAC-n Latch and updates the output for all DAC-n with the corresponding SLDA-n bit set to

'1'. Other codes written to this register do not generate ILDAC and have no impact on any DAC-n. The LOAD

DAC Register is cleared after ILDAC is generated. The register is also cleared after power-on or reset.

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