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DRV8428DYYR bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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DRV8428DYYR bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 53 page ![]() 8 DRV8428 SLOSE54 – JUNE 2020 www.ti.com Product Folder Links: DRV8428 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RDS(ONL) Low-side FET on resistance VVM = 24 V, TJ = 25 °C, IO = 0.5 A 750 900 m Ω VVM = 24 V, TJ = 125 °C, IO = 0.5 A 1130 1400 m Ω VVM = 24 V, TJ = 150 °C, IO = 0.5 A 1250 1590 m Ω tSR Output slew rate VVM = 24 V, IO = 0.5 A, Between 10% and 90% 240 V/µs PWM CURRENT CONTROL (VREF) KV Transimpedance gain VREF = 3 V 2.85 3 3.15 V/A tOFF PWM off-time, mixed 30% decay DECAY/TOFF = 14.7 kΩ to GND 7 μs DECAY/TOFF = 44.2 kΩ to GND 16 DECAY/TOFF = 100 kΩ to GND 32 PWM off-time, Smart tune dynamic decay DECAY/TOFF = 249 kΩ to GND 7 DECAY/TOFF = Hi-Z 16 DECAY/TOFF = Tied to DVDD 32 ΔITRIP Current trip accuracy IO = 1 A, 10% to 20% current setting –15 15 % IO = 1 A, 20% to 67% current setting –10 10 IO = 1 A, 68% to 100% current setting –5 5 IO,CH AOUT and BOUT current matching IO = 1 A –2.5 2.5 % PROTECTION CIRCUITS VUVLO VM UVLO lockout VM falling, UVLO falling 3.85 3.95 4.05 V VM rising, UVLO rising 3.95 4.05 4.15 VUVLO,HYS Undervoltage hysteresis Rising to falling threshold 100 mV IOCP Overcurrent protection Current through any FET 1.7 A tOCP Overcurrent deglitch time 1.25 μs TOTSD Thermal shutdown Die temperature TJ 150 165 180 °C THYS_OTSD Thermal shutdown hysteresis Die temperature TJ 20 °C (1) STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load. 6.6 Indexer Timing Requirements Typical limits are at TJ = 25°C and VVM = 24 V. Over recommended operating conditions unless otherwise noted. NO. MIN MAX UNIT 1 ƒSTEP Step frequency 500(1) kHz 2 tWH(STEP) Pulse duration, STEP high 970 ns 3 tWL(STEP) Pulse duration, STEP low 970 ns 4 tSU(DIR, Mx) Setup time, DIR or MODEx to STEP rising 200 ns 5 tH(DIR, Mx) Hold time, DIR or MODEx to STEP rising 200 ns |
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