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54HC74 bảng dữ liệu(PDF) 3 Page - Motorola, Inc

tên linh kiện 54HC74
Giải thích chi tiết về linh kiện  Dual D-Type Flip-Flop with Set and Reset
PDF  6 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

54HC74 bảng dữ liệu(HTML) 3 Page - Motorola, Inc

  54HC74 Datasheet HTML 1Page - Motorola, Inc 54HC74 Datasheet HTML 2Page - Motorola, Inc 54HC74 Datasheet HTML 3Page - Motorola, Inc 54HC74 Datasheet HTML 4Page - Motorola, Inc 54HC74 Datasheet HTML 5Page - Motorola, Inc 54HC74 Datasheet HTML 6Page - Motorola, Inc  
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MC74VHC74
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
3
MOTOROLA
DC ELECTRICAL CHARACTERISTICS
Unit
TA = – 40 to 85°C
TA = 25°C
VCC
V
Test Conditions
Parameter
Symbol
Unit
Max
Min
Max
Typ
Min
VCC
V
Test Conditions
Parameter
Symbol
Iin
Maximum Input
Leakage Current
Vin = 5.5V or GND
0 to 5.5
± 0.1
± 1.0
µA
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
2.0
20.0
µA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Sb l
P
T
C
di i
TA = 25°C
TA = – 40 to 85°C
Ui
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
tPLH,
tPHL
Maximum Propagation Delay,
CP to Q or Q
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
6.7
9.2
11.9
15.4
1.0
1.0
14.0
17.5
ns
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.6
6.1
7.3
9.3
1.0
1.0
8.5
10.5
tPLH,
tPHL
Maximum Propagation Delay,
SD or RD to Q or Q
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
7.6
10.1
12.3
15.8
1.0
1.0
14.5
18.0
ns
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.8
6.3
7.7
9.7
1.0
1.0
9.0
11.0
fmax
Maximum Clock Frequency
(50% Duty Cycle)
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
80
50
125
75
70
45
MHz
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
130
90
170
115
110
75
Cin
Maximum Input Capacitance
4
10
10
pF
C
PDi
i
i
C
i
(N
1 )
Typical @ 25
°C, VCC = 5.0V
F
CPD
Power Dissipation Capacitance (Note 1.)
25
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 2 (per flip–flop). CPD is used to determine the
no–load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Sb l
P
V
Guaranteed Limit
Ui
Symbol
Parameter
VCC
V
TA = 25_C
TA = – 40 to
85
_C
Unit
tw
Minimum Pulse Width, CP
3.3
± 0.3
5.0
± 0.5
6.0
5.0
7.0
5.0
ns
tw
Minimum Pulse Width, RD or SD
3.3
± 0.3
5.0
± 0.5
6.0
5.0
7.0
5.0
ns
tsu
Minimum Setup Time, D to CP
3.3
± 0.3
5.0
± 0.5
6.0
5.0
7.0
5.0
ns
th
Minimum Hold Time, D to CP
3.3
± 0.3
5.0
± 0.5
0.5
0.5
0.5
0.5
ns
trec
Minimum Recovery Time, SD or RD to CP
3.3
± 0.3
5.0
± 0.5
5.0
3.0
5.0
3.0
ns



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