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TMS320VC5502 bảng dữ liệu(PDF) 30 Page - Texas Instruments |
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TMS320VC5502 bảng dữ liệu(HTML) 30 Page - Texas Instruments |
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30 / 195 page ![]() TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166K – APRIL 2001 – REVISED NOVEMBER 2008 www.ti.com Table 2-4. Signal Descriptions (continued) PIN MULTIPLEXED PIN OTHER(2) FUNCTION NAME SIGNAL NAME TYPE(1) Multichannel Buffered Serial Port Pins (McBSP0 and McBSP1) C, F, G, H, Receive clock input of McBSP0. The CLKR0 pin is configured as an input after CLKR0 I/O/Z M reset. DR0 I L, G Serial data receive input of McBSP0 Frame synchronization pulse for receive input of McBSP0. The FSR0 pin is FSR0 I/O/Z F, G, H, M configured as an input after reset. C, F, G, H, CLKX0 I/O/Z Transmit clock of McBSP0. The CLKX0 pin is configured as an input after reset. M Serial data transmit output of McBSP0. The DX0 pin is in a high-impedance state DX0 O/Z F, H, M during and after reset. Frame synchronization pulse for transmit output of McBSP0. The FSX0 pin is FSX0 I/O/Z F, G, H, M configured as an input after reset. Receive clock input of McBSP1. The CLKR1 pin is configured as an input after CLKR1 I/O/Z C, G, H, M reset. DR1 I L, G Serial data receive input of McBSP1 Frame synchronization pulse for receive input of McBSP1. The FSR1 pin is FSR1 I/O/Z F, G, H, M configured as an input after reset. Serial data transmit output of McBSP1. The DX1 pin is in a high-impedance state DX1 O/Z F, H, M during and after reset. C, F, G, H, CLKX1 I/O/Z Transmit clock of McBSP1. The CLKX1 pin is configured as an input after reset. M Frame synchronization pulse for transmit output of McBSP1. The FSX1 pin is FSX1 I/O/Z F, G, H, M configured as an input after reset. Serial Port 2 (McBSP2/UART) Pins DR2 I L, G McBSP2 data receive input McBSP2 data transmit output. The DX2 pin is in a high-impedance state during DX2 O/Z F, H, M and after reset. The SP0 pin of Serial Port 2 serves one of two functions: GPIO3 or CLKX2. The function of the SP0 pin is determined by the state of the GPIO7 pin during reset. SP0 I/O/Z C, F, M The SP0 pin is set to GPIO3 if GPIO7 is low during reset. The SP0 pin is set to CLKX2 if GPIO7 is high during reset. The function of the SP0 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). GPIO3. GPIO3 is selected if GPIO7 is low during reset. The GPIO3 signal is GPIO3 I/O/Z G, H configured as input after reset. McBSP2 transmit clock. CLKX2 is selected if GPIO7 is high during reset. The CLKX2 I/O/Z G, H CLKX2 signal is configured as input after reset. The SP1 pin of Serial Port 2 serves one of two functions: UART.TX or CLKR2. The function of the SP1 pin is determined by the state of the GPIO7 pin during reset. SP1 I/O/Z C, F, M The SP1 pin is set to UART.TX if GPIO7 is low during reset. The SP1 pin is set to CLKR2 if GPIO7 is high during reset. The function of the SP1 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). UART transmit data output. UART.TX is selected if GPIO7 is low during reset. The UART.TX O UART.TX signal outputs a value of 1 during and after reset. McBSP2 receive clock. CLKR2 is selected if GPIO7 is high during reset. The CLKR2 I/O/Z G, H CLKR2 signal is configured as input after reset. The SP2 pin of Serial Port 2 serves one of two functions: GPIO5 or FSX2. The function of the SP2 pin is determined by the state of the GPIO7 pin during reset. SP2 I/O/Z F, M The SP2 pin is set to GPIO5 if GPIO7 is low during reset. The SP2 pin is set to FSX2 if GPIO7 is high during reset. The function of the SP2 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). GPIO5. GPIO5 is selected if GPIO7 is low during reset. The GPIO5 signal is GPIO5 I/O/Z G, H configured as input after reset. Frame synchronization pulse for transmitter of McBSP2. FSX2 is selected if FSX2 I/O/Z G, H GPIO7 is high during reset. The FSX2 signal is configured as input after reset. Introduction 30 Submit Documentation Feedback |
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