HSP50214VC datasheet(13/54 Pages) INTERSIL

13 / 54 page

Each serial word has a programmable word width of either 8,

16, 24, or 32 bits (See Control Word 0, bits 4 and 5, for the

Carrier NCO programming and Control Word 11, bits 3 and

4, for Timing NCO programming). On the rising edge of the

clock, data on COF or SOF is clocked into an input shift reg-

ister. The beginning of a serial word is designated by assert-

ing either COFSYNC or SOFSYNC “high” one CLK period

prior to the ﬁrst data bit.

The assertion of the COFSYNC (or SOFSYNC) starts a count

down from the programmed word width. On following CLKs,

data is shifted into the register until the speciﬁed number of

bits have been input. At this point the contents of the register

are transferred from the shift register to the respective 32-bit

holding register. The shift register can accept new data on the

following CLK. If the serial input word is deﬁned to be less

than 32 bits, it will be transferred to the MSBs of the 32-bit

holding register and the LSBs of the holding register will be

zeroed. See Figure 14 for details.

NOTE: Serial Data must be loaded MSB first, and COFSYNC or

SOFSYNC should not be asserted for more than one CLK

cycle.

NOTE: COF loading and timing is relative to CLKIN while SOF

loading and timing is relative to PROCCLK.

NOTE: TD can be 0, and the fastest rate is with 8-bit word width.

CIC Decimation Filter

The mixer output may be ﬁltered with the CIC ﬁlter or it may be

routed directly to the halfband ﬁlters. The CIC ﬁlter is used to

reduce the sample rate of a wideband signal to a rate that the

halfbands and programmable ﬁlters can process, given the

maximum computation speed of PROCCLK. (See Halfband

and FIR Filter Sections for techniques to calculate this value.)

Prior to the CIC ﬁlter, the output of the mixer goes through a

barrel shifter. The shifter is used to adjust the gain in 6dB

steps to compensate for the variation in ﬁlter gain with deci-

mation. (See Equation 6). Fine gain adjustments must be

done in the AGC section. The shifter is controlled by the sum

of a 4-bit CIC Shift Gain word from the microprocessor and a

3-bit gain word from the GAINADJ(2:0) pins. The three bit

value is pipelined to match the delay of the input samples.

The sum of the 3 and 4-bit shift gain words saturates at a

value of 15. Table 3 details the permissible values for the

GAINADJ(2:0) barrel shifter control, while the Figure 15

shows the permissible CIC Shift Gain values.

The CIC ﬁlter structure for the HSP50214 is ﬁfth order; that

is it has ﬁve integrator/comb pairs. A ﬁfth order CIC has

84dB of alias attenuation for output frequencies below 1/8

the CIC output sample rate.

The decimation rate of the CIC ﬁlter is programmed in Control

Word 0, bits 12 - 7. The CIC Shift Gain is programmed in Con-

trol Word 0, bits 16-13. The CIC Bypass is set in Control Word

0, bit 6.

COF/

MSB

CLKIN

COFSYNC/

SOFSYNC

SOF

LSB

OTE:

Data must be loaded MSB first.

IGURE 13. SERIAL INPUT TIMING FOR COF AND SOF INPUTS

†Serial word width can be: 8, 16, 24, 32 bits wide.

†TD is determined by the COFSYNC, COFSYNC rate.

FIGURE 14. HOLDING REGISTERS LOAD SEQUENCE FOR

COF AND SOF SERIAL OFFSET FREQUENCY

DATA

†

DATA TRANSFERRED

TO HOLDING REGISTER

TD††

CLK TIMES

ASSERTION OF

COFSYNC, SOFSYNC

(8)

(32)

(16)

(24)

TABLE 3. GAIN ADJUST CONTROL AND CIC DECIMATION

∆GAIN VALUE

(dB)

GAIN ADJ(2:0)

MAX. CIC

DECIMATION

000

001

010

011

100

101

110

111

FIGURE 15. CIC SHIFT GAIN VALUES

440

DECIMATION (R)

122028364452

8-BIT INPUT

12-BIT INPUT

10-BIT INPUT

14-BIT INPUT

ALLOWABLE CIC SHIFT

GAINS ARE BELOW THE

CURVES

HSP50214

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