7-848

CD4034BMS

Applications

FIGURE 12. 16-BIT PARALLEL IN/PARALLEL OUT, PARALLEL IN/SERIAL OUT,

SERIAL IN/PARALLEL OUT SERIAL IN/SERIAL OUT REGISTER

FIGURE 13. 16-BIT SERIAL IN/GATED PARALLEL OUT REGISTER

FIGURE 14. SINGLE AND DOUBLE-BUS SYSTEMS

A PARALLEL

DATA

B PARALLEL

DATA

SERIAL

DATA

AE

SI

A/B

A/S

CL

P/S

SERIAL

DATA

VDD

P/S

A/S

CL

VDD

A PARALLEL

DATA

B PARALLEL

DATA

SERIAL

DATA

AE

SI

A/B

A/S

CL

P/S

VDD

VDD

CD4034

CD4034

A PARALLEL

DATA

B PARALLEL

DATA

SERIAL

DATA

AE

SI

A/B

A/S

CL

P/S

SERIAL

DATA

A/B

CL

“A” ENABLE

A PARALLEL

DATA

B PARALLEL

DATA

SERIAL

DATA

AE

SI

A/B

A/S

CL

P/S

CD4034

CD4034

MEMORY

UNIT

PERIPHERAL

UNIT

W REG

P/S

1

2

3

4

5

6

7

8

SI

A/B A/S CL

1

2

3

4

5

6

7

8

AE

B

A

Y REG

P/S

1

2

3

4

5

6

7

8

SI

A/B A/S CL

1

2

3

4

5

6

7

8

AE

B

A

Z REG

AE

1

2

3

4

5

6

7

8

SI

A/B A/S CL

1

2

3

4

5

6

7

8

P/S

A

B

AE

P/S

SI A/B A/S CL

1

2

3

4

5

6

7

8

A

1

2

3

4

5

6

7

8

B

REG

X(1)

P/S

AE

SI A/B A/S CL

1

2

3

4

5

6

7

8

B

1

2

3

4

5

6

7

8

A

REG

X(2)

ARITHMETIC

UNIT

TO 2ND

BUS

SYSTEM

DOUBLE - BUS SYSTEM

(ENABLE INPUTS ON BOTH SIDES)

THE “A” ENABLE (AE) AND A/B SIGNALS CONTROL ALL

COMBINATIONS OF TRANSFER BETWEEN THE REGISTERS

AND BUS SYSTEMS

CD4034

CD4034

CD4034

CD4034

CD4034

BUS LINES

(SINGLE)