M58LT128GS datasheet(35/98 Pages) STMICROELECTRONICS

35 / 98 page

M58LT128GST, M58LT128GSB

6 Configuration Register

35/98

Configuration Register

The Configuration Register is used to configure the type of bus access that the memory will

perform. Refer to Read Modes section for details on read operations.

The Configuration Register is set through the Command Interface using the Set Configuration

(CR15 = 1). The Configuration Register bits are described in Table 10 They specify the

selection of the burst length, burst type, burst X latency and the read operation. Refer to

Figure 5 and Figure 6 for examples of synchronous burst configurations.

6.1

Read Select Bit (CR15)

The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read

operations.

When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read

Select bit is set to ’0’, read operations are synchronous.

Synchronous Burst Read is supported in both parameter and main blocks and can be

performed across banks.

On reset or power-up the Read Select bit is set to ’1’ for asynchronous access.

6.2

X-Latency Bits (CR13-CR11)

The X-Latency bits are used during Synchronous Read operations to set the number of clock

cycles between the address being latched and the first data becoming available. For correct

operation the X-Latency bits can only assume the values in Table 10: Configuration Register.

The correspondence between X-Latency settings and the maximum sustainable frequency

must be calculated taking into account some system parameters. Two conditions must be

satisfied:

Depending on whether tAVK_CPU or tDELAY is supplied either one of the following two

equations must be satisfied:

(n + 1) tK ≥ tAVQV - tAVK_CPU + tQVK_CPU

(n + 2) tK ≥ tAVQV + tDELAY + tQVK_CPU

and also

tK > tKQV + tQVK_CPU

where

●

n is the chosen X-Latency configuration code

●

tK is the clock period

●

tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last

●

tDELAY is address valid, L Low, or E Low to clock, whichever occurs last

●

tQVK_CPU is the data setup time required by the system CPU,

●

tKQV is the clock to data valid time

●

tAVQV is the random access time of the device.

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