1

0

N-1

N-2

Left (Ch1)

Slot-0

(Word Length : 32)

1

0

N-1

N-2

BCLK

SDOUT

n

(n+1)

1

0

N-1

Right (Ch2)

Slot-0

(Word Length : 32)

Left (Ch1)

Slot-0

(Word Length : 32)

FSYNC

N-2

1

0

N-1

N-2

BCLK

SDOUT

n

(n+1)

1

0

N-1

FSYNC

N-2

1

0

1

0

N-1

N-2

1

0

N-1

N-2

Left (Ch1)

Slot-0

(Word Length : 32)

Right (Ch2)

Slot-0

(Word Length : 32)

Left (Ch1)

Slot-0

(Word Length : 32)

Right (Ch2)

Slot-0

(Word Length : 32)

1

0

N-1

N-2

1

0

N-1

N-2

BCLK

SDOUT

n

(n+1)

1

0

N-1

FSYNC

N-2

Left (Ch1)

Slot-0

(Word Length : 32)

Right (Ch2)

Slot-0

(Word Length : 32)

Left (Ch1)

Slot-0

(Word Length : 32)

13

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equal to the number of active output channels (including left and right slots) times the 32-bits word length of the

output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater than or

equal to the number of active left slots times the 32-bits data word length. Similarly, the FSYNC high pulse must

be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the 32-

bits data word length. The device transmit zero data value on SDOUT for the extra unused bit clock cycles.

7.3.2.3 Left-Justified (LJ) Interface

The standard LJ protocol is defined for only two channels: left and right. In LJ mode, the MSB of the left slot 0 is

transmitted in the same BCLK cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on

the falling edge of BCLK. The MSB of the right slot 0 is transmitted in the same BCLK cycle after the falling edge

of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. In master mode, FSYNC is

transmitted on the rising edge of BCLK. Figure 20 and Figure 21 illustrate the protocol timing for LJ operation in

slave and master mode of operation.

Figure 20. LJ Mode Protocol Timing In Slave Mode