TMS320UC5405 datasheet(21/77 Pages) TI

21 / 77 page

Functional Overview

October 2002 − Revised October 2004

SPRS199B

3.1.3 Memory Map

Page 0 Program

Hex

Data

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

MP/MC= 0

(Microcomputer Mode)

MP/MC= 1

(Microprocessor Mode)

0000

007F

0080

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

Memory

Mapped

Registers

On-Chip DARAM

(16K x 16-bit)

ROM (DROM=1)

or External†

(DROM=0)

0080

FFFF

Hex

0000

FF00

FEFF

EFFF

F000

FFFF

3FFF

4000

0060

007F

0000

Hex

Page 0 Program

External†

Scratch-Pad

RAM

Reserved

(DROM=1)

or External

(DROM=0)

005F

Reserved

(OVLY = 1)

External

(OVLY = 0)

007F

0080

3FFF

4000

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

FF00

FEFF

EFFF

F000

On-Chip ROM

(4K x 16-bit)

Interrupts

(On-Chip)

3FFF

4000

Reserved

FF7F

FF80

External†

FF7F

FF80

Reserved

† Only six of the 16 total TMS320UC5405 address bits are available to the external interface; therefore, only 64 unique external addresses are

available, regardless of the actual 16-bit address generated internally. These 64 addresses are those resulting from the truncation of the upper

address bits (A6 and above). This results in these 64 addresses being repeated throughout all of the external address space.

Figure 3−2. TMS320UC5405 Memory Map

3.1.4 Implications of 6-Bit Addressing

TMS320UC5405 provides only six of the 16 total address bits to the external interface. Therefore, only

64 unique external addresses are available, regardless of the actual 16-bit address generated internally.

These 64 addresses are those resulting from the truncation of the upper address bits (A6 through A15). This

results in these 64 addresses being repeated throughout all of the external address space.

If more than 64 external locations need to be addressed, a paging scheme can be used to expand the

addressing capability as necessary. In this paging scheme, an external register is used to supply the upper

addresses (A6 through A15) for the memory reach greater than six bits. The external register is loaded by

having the 5405 write to a location in I/O space whose data lines are the higher address bits as shown in

Figure 3−3. This scheme can be implemented using either a simple external latch, or can be included in a

FPGA. This paging scheme can be implemented without any decoding required and shares the same bus

with the SRAM and the DSP.

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