SL2S1502FUD datasheet(9/33 Pages) NXP

9 / 33 page

NXP Semiconductors

SL2S1402_SL2S1502_SL2S1602

ICODE ILT

SL2S1402_SL2S1502_SL2S1602

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.3 — 15 October 2019

COMPANY PUBLIC

234333

9 / 33

8 Mechanical specification

8.1 Wafer specification

See Ref. 13 "General specification for 8" wafer on UV-tape with electronic fail die

marking".

Table 4. Wafer specification

Wafer

Designation

each wafer is inscribed with batch number and wafer number

Diameter

200 mm (8 inches)

Thickness

SL2S1402FUD/

SL2S1502FUD/

SL2S1602FUD

120 μm ± 15 μm

SL2S1402FUF/SL2S1502FUF 75 μm ± 15 μm

Process

CMOS 0.14 μm

Batch size

25 wafers

Dies per wafer

SL2S1402FUx/SL2S1502FUx 110050

SL2S1602FUD

88225

Wafer backside

Material

Treatment

ground and stress release

Ra minimum = 0.5 μm

Roughness

Rt maximum = 5 μm

Chip dimensions

Die size without scribe

SL2S1402FUx/SL2S1502FUx 520 μm × 484 μm = 251680 μm2

SL2S1602FUD

520 μm × 607 μm = 315640 μm2

Scribe line width

X-dimension

15 μm (scribe line width measured between nitride edges)

Y-dimension

15 μm (scribe line width measured between nitride edges)

Number of pads

Pad location

non-diagonal/placed in chip corners

Distance pad to pad LA to LB

400 μm

Distance pad to pad LB to TEST

SL2S1402FUx/SL2S1502FUx 360 μm

SL2S1602FUD

517 μm

Passivation on front

SL2S1502FUD bảng dữ liệu(PDF) 9 Page - NXP Semiconductors

SL2S1502FUD bảng dữ liệu(HTML) 9 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

bảng dữ liệu tải về

Link URL