AX68002QF datasheet(26/57 Pages) ASIX

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AX6800x

2/4-Port USB KVM Switch SoC

2.5 Memory Controller and On-Chip Data Memory

AX6800x supports xDATA memory of CPU up to 32K bytes.

The Memory Arbiter – provides fair access arbitration for xDATA memory (on-chip 32KB Data SRAM) among

CPU and the DMA Controllers.

2.6 DMA Controller

The DMA Controllers support direct xDATA memory (on-chip 32KB Data SRAM) read and write access without

CPU intervention for the USB Host Controller, USB Device Controller, High Speed SPI, I2C, High Speed UART

1, as well as bulk data copy for Software DMA.

2.7 Interrupt Controller

The Interrupt Controller supports one external interrupt pin, INT0, having two levels of interrupt priority control.

They can be in high or low-level priority group (set via IP and EIP SFR register). The INT0 external interrupt pins

can be either low-level trigger or falling-edge trigger. Also, the Interrupt Controller supports various interrupt

requests internal to AX6800x, again each having two levels of interrupt priority control.

2.8 Watchdog Timer

The Watchdog Timer is a user programmable clock counter that can serve as:



A time-base generator



An event timer



System supervisor

The watchdog timer runs on the operating system clock, which supplies to a series of dividers. The divider output

is selectable, and determines interval between timeouts.

When the timeout is reached, an interrupt flag will be set, and if enabled, a reset will occur (to reset CPU core). The

interrupt flag will cause an interrupt to occur if enabled. The reset and interrupt are discrete functions that may be

acknowledged or ignored, together or separately for various applications.

AX68002QF bảng dữ liệu(PDF) 26 Page - ASIX Electronics Corporation