UCD8620PWPR datasheet(7/32 Pages) TI

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VIT−

10%

90%

INPUT

OUTPUT

VIT+

t D1

t D2

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS (continued)

DD = 12 V, 4.7-µF capacitor from VDD to AGND, 1 µF from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND,

A = TJ = -40°C to 105°C, (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ISET resistor range

Current mode control; RISET connected to AGND

6.19

499

Ω

ISET resistor range

Voltage mode control; RISET connected to 3V3

4.99

402

Voltage mode control with Feed-Forward; RISET connected to

ISET current range

3.7

300

µA

VIN

PWM

PWM offset at CTRL input

3V3 = 3.3 V +/-2%

0.45

0.51

0.6

CTRL buffer gain(1)

Gain from CTRL to PWM comparator input

0.5

V/V

CURRENT LIMIT (ILIM)

ILIM internal current limit threshold

ILIM = OPEN

0.466

0.5

0.536

ILIM maximum current limit threshold

ILIM = 3.3 V

0.975

1.025

1.075

ILIM current limit threshold

ILIM = 0.75 V

0.700

0.725

0.750

ILIM minimum current limit threshold

ILIM = 0.25 V

0.21

0.23

0.25

CLF output high level

CS > ILIM , ILOAD = -7 mA

2.64

CLF output low level

≤ ILIM, I

LOAD = 7 mA

0.66

Propagation delay from CLK to CLF

CLK rising to CLF falling after a current limit event

CURRENT SENSE COMPARATOR

Bias voltage

Includes CS comp offset

Input bias current

–1

µA

Propagation delay from CS to OUTx

ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV

Propagation delay from CS to CLF

ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV

CURRENT SENSE DISCHARGE TRANSISTOR

Discharge resistance

CLK = low, resistance from CS to AGND

Ω

OUTPUT DRIVERS

Source current (2)

VDD = 12 V, CLK = high, OUTx = 5 V

Sink current (2)

VDD = 12 V, CLK = low, OUTx = 5 V

Source current(2)

VDD = 4.75 V, CLK = high, OUTx = 0

Sink current (2)

VDD = 4.75 V, CLK = low, OUTx = 4.75 V

Rise time, tR

CLOAD = 2.2 nF, VDD = 12 V

Fall time, tF

CLOAD = 2.2 nF, VDD = 12 V

Output with VDD < UVLO

VDD = 1.0 V, ISINK = 10 mA

0.8

1.2

CLOAD = open, VDD = 12 V, CLK rising, tD1

Propagation delay from CLK to OUTx

CLOAD = open, VDD = 12 V, CLK falling, tD2

(2)

Ensured by design. Not 100% tested in production.

Figure 5. Timing Diagram

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