6

Timing Diagram

Definition of Terms

TERM

DEFINITION

Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output

Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications

Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the

CMOS logic threshold of an output low to high transition

Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the

CMOS logic threshold of an output high to low transition

Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low

to high transition to the point of the output crossing CMOS threshold in a low to high transition

Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low

to high transition to the point of the output crossing CMOS threshold in a high to low transition

Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be

present in order to be acquired and held at the outputs

Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged

in order to be acquired and held at the output

Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an

input signal change

Latch

Enable

Input

Latch

Compare

Latch

Latch

Compare

Differential

Input

Voltage

Comparator

Output

1.4V

2.4V

EL5481, EL5482