CY25811/12/14
Document #: 38-07112 Rev. *E
Page 5 of 11
AC Electrical Specifications (Commercial Grade)
Parameter
Description
Condition
Min.
Max.
Unit
FIN
Input Frequency Range
Clock, Crystal or Ceramic Resonator Input
4
32
MHz
TR1
Clock Rise Time
SSCLK, CY25811 and CY25812
2.0
5.0
ns
TF1
Clock Fall Time
SSCLK, CY25811 and CY25812
2.0
4.4
ns
TR2
Clock Rise Time
SSCLK, only CY25814 when FRSEL = M
1.0
2.2
ns
TF2
Clock Fall Time
SSCLK, only CY25814 when FRSEL = M
1.0
2.2
ns
TDCIN
Input Clock Duty Cycle
XIN
40
60
%
TDCOUT
Output Clock Duty Cycle
SSCLK
40
60
%
TCCJ1
Cycle-to-Cycle Jitter, Spread on
Fin = 4 MHz, Fout = 4 MHz, CY25811
–
800
ps
TCCJ2
Cycle-to-Cycle Jitter, Spread on
Fin = 8 MHZ, Fout = 8 MHz, CY25811
–
450
ps
TCCJ3
Cycle-to-Cycle Jitter, Spread on
Fin = 8 MHz, Fout = 16 MHz, CY25812
–
400
ps
TCCJ4
Cycle-to-Cycle Jitter, Spread on
Fin = 16 MHz, Fout = 32 MHz, CY25812
–
380
ps
TCCJ5
Cycle-to-Cycle Jitter, Spread on
Fin = 16 MHz, Fout = 64 MHz, CY25814
–
380
ps
TCCJ6
Cycle-to-Cycle Jitter, Spread on
Fin = 32 MHz, Fout = 128 MHz, CY25814
–
380
ps
TSU
PLL Lock Time
Fom VDD 3.0V to valid SSCLK
–
3
ms
DC Electrical Specifications (Industrial Grade)
Parameter
Description
Condition
Min.
Max.
Unit
VDD
3.3 Operating Voltage
3.3 ± 5%
3.135
3.465
V
VIL
Input Low Voltage
S0, S1 and FRSEL Inputs
0
0.13VDD
V
VIM
Input Middle Voltage
S0, S1 and FRSEL Inputs
0.40VDD 0.60VDD
V
VIH
Input High Voltage
S0, S1 and FRSEL Inputs
0.85VDD
VDD
V
VOL1
Output Low Voltage
IOL = 4 ma, SSCLK Output
–
0.4
V
VOL2
Output Low Voltage
IOL = 10 ma, SSCLK Output
–
1.2
V
VOH1
Output High Voltage
IOH = 4 ma, SSCLK Output
2.4
–
V
VOH2
Output High Voltage
IOH = 6 ma, SSCLK Output
2.0
–
V
CIN1
Input Pin Capacitance
XIN (Pin 1) and XOUT (Pin 8)
6.0
9.0
pF
CIN2
Input Pin Capacitance
All Digital Inputs
3.5
6.0
pF
CL
Output Load Capacitor
SSCLK Output
–
15
pF
IDD1
Dynamic Supply Current
Fin = 12 MHz, no load
–
26
mA
IDD2
Dynamic Supply Current
Fin = 24 MHz, no load
–
32
mA
IDD3
Dynamic Supply Current
Fin = 32 MHz, no load
–
37
mA
AC Electrical Specifications (Industrial Grade)
Parameter
Description
Condition
Min.
Max.
Unit
FIN
Input Frequency Range
Clock, Crystal or Ceramic Resonator Input
4
32
MHz
TR1
Clock Rise Time
SSCLK, CY25811 and CY25812
2.0
5.0
ns
TF1
Clock Fall Time
SSCLK, CY25811 and CY25812
2.0
4.4
ns
TR2
Clock Rise Time
SSCLK, only CY25814 when FRSEL = M
1.0
2.2
ns
TF2
Clock Fall Time
SSCLK, only CY25814 when FRSEL = M
1.0
2.2
ns
TDCIN
Input Clock Duty Cycle
XIN
40
60
%
TDCOUT
Output Clock Duty Cycle
SSCLK
40
60
%
TCCJ1
Cycle-to-Cycle Jitter, Spread on
Fin = 6MHz, CY25811/12/14
–
650
ps
TCCJ2
Cycle-to-Cycle Jitter, Spread on
Fin = 12MHZ, CY25811/12/14
–
400
ps
TCCJ3
Cycle-to-Cycle Jitter, Spread on
Fin = 24MHz, CY25811/12/14
–
400
ps
TSU
PLL Lock Time
From VDD 3.0V to valid SSCLK
–
4
ms
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
