AD7877 datasheet(21/44 Pages) AD

21 / 44 page

AD7877

Rev. A | Page 21 of 44

Table 6. Codes for Selecting Input Channel and Normal or Ratiometric Conversion

Channel

SER/DFR

CHADD(3:0)

Analog Input

X Switches

Y Switches

+REF

−REF

0 0 0 0

X+ (Y Position)

OFF

Y+

Y−

0 0 0 1

Y+ (X Position)

OFF

X+

X−

0 0 1 0

Y− (Z2)

X+ OFF, X− ON

Y+ ON, Y− OFF

Y+

X−

0 01 1

AUX1

OFF

VREF

GND

0 1 00

AUX2

OFF

VREF

GND

0 1 0 1

AUX3

OFF

VREF

GND

0 1 1 0

BAT1

OFF

VREF

GND

0 1 1 1

BAT2

OFF

VREF

GND

1 0 0 0

TEMP1

OFF

VREF

GND

1 0 0 1

TEMP2

OFF

VREF

GND

1 0 1 0

X+ (Z1)

X+ OFF, X− ON

Y+ ON, Y− OFF

Y+

X−

1 0 1 1

INVALID ADDRESS

1 1 0 0

INVALID ADDRESS

1 1 0 1

INVALID ADDRESS

1 1 1 0

INVALID ADDRESS

1 1 1 1

INVALID ADDRESS

0 0 0 0

X+ (Y Position)

OFF

VREF

GND

0 0 0 1

Y+ (X Position)

OFF

VREF

GND

0 0 1 0

Y− (Z2)

X+ OFF, X− ON

Y+ ON, Y− OFF

VREF

GND

0 0 1 1

AUX1

OFF

VREF

GND

0 1 0 0

AUX2

OFF

VREF

GND

0 1 0 1

AUX3

OFF

VREF

GND

0 1 1 0

BAT1

OFF

VREF

GND

0 1 1 1

BAT2

OFF

VREF

GND

1 0 0 0

TEMP1

OFF

VREF

GND

1 0 0 1

TEMP2

OFF

VREF

GND

1 0 1 0

X+ (Z1)

X+ OFF, X− ON

Y+ ON, Y− OFF

VREF

GND

10 1 1

INVALID ADDRESS

1 1 0 0

INVALID ADDRESS

1 1 0 1

INVALID ADDRESS

1 1 1 0

INVALID ADDRESS

1 1 1 1

INVALID ADDRESS

CONTROL REGISTER 2

Timer (Control Register 2 Bits <1:0>)

The TMR bits in Control Register 2 enable the ADC to

repeatedly perform a conversion or conversion sequence either

once only or at intervals of 512 µs, 1.024 ms, or 8.19 ms. In slave

mode, the timer starts as soon as the conversion sequence is

finished. In master mode, the timer starts at the end of a conver-

sion sequence only if the screen remains touched. If the touch is

released at any stage, then the timer stops and, the next time the

screen is touched, a conversion sequence begins immediately.

Table 7. Control Register 2 Timer Selection

TMR1

TMR0

Function

Convert only once (default)

Every 1024 clocks (512 µs)

Every 2048 clocks (1.024 ms)

Every 16,384 clocks (8.19 ms)

Int/Ext Reference (Control Register 2 Bit <2>)

If the REF bit in Control Register 2 is 0 (default value), the

internal reference is selected. If any connection is made to VREF

while the internal reference is selected (for example, to supply a

reference to other circuits), it should be buffered. An external

power supply should not be connected to this pin while REF is

equal to 0, because it might overdrive the internal reference.

Note also that, because the internal reference is 2.5 V, it operates

only with supply voltages down to 2.7 V. Below this value an

external reference should be used.

If the REF bit is 1, the VREF pin becomes an input and the

internal reference is powered down. This overrides any setting

of the PM bits with regard to the reference. An external

reference can then be applied to the REF pin.

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