ST92195D7 datasheet(60/249 Pages) STMICROELECTRONICS

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ST92195C/D - RESET AND CLOCK CONTROL UNIT (RCCU)

4 RESET AND CLOCK CONTROL UNIT (RCCU)

4.1 INTRODUCTION

The Reset Control Unit comprises two distinct sec-

tions:

– An oscillator that uses an external quartz crystal.

– The Reset/Stop Manager, which detects and

flags Hardware, Software and Watchdog gener-

ated resets.

4.2 RESET / STOP MANAGER

The RESET/STOP Manager resets the device

when one of the three following triggering events

occurs:

– A hardware reset, consequence of a low level on

the RESET pin.

– A software reset, consequence of an HALT in-

struction when enabled.

– A Watchdog end of count.

The RESET input is schmitt triggered.

Note: The memorized Internal Reset (called RE-

SETO) will be maintained active for a duration of

32768 Oscin periods (about 8 ms for a 4 MHz crys-

tal) after the external input is released (set high).

This RESETO internal Reset signal is output on

the I/O port bit P3.7 (active low) during the whole

reset phase until the P3.7 configuration is changed

by software. The true internal reset (to all macro-

cells) will only be released 511 Reference clock

periods after the Memorized Internal reset is re-

leased.

It is possible to know which was the last RESET

triggering event, by reading bits 5 and 6 of register

SDRATH.

Figure 28. Reset Overview

4.3 OSCILLATOR CHARACTERISTICS

The on-chip oscillator circuit uses an inverting gate

circuit with tri-state output.

Notes:

Owing to the Q factor required, Ceramic Resona-

tors may not provide a reliable oscillator source.

The oscillator can not support quartz crystal or ce-

ramic working at the third harmonic without exter-

nal tank circuits.

OSCOUT must not be used to drive external cir-

cuits.

Halt mode is set by means of the HALT instruction.

In this mode the parallel resistor, R, is disconnect-

ed and the oscillator is disabled. This forces the in-

ternal clock to a high level and OSCOUT to a high

impedance state.

To exit the HALT condition and restart the oscilla-

tor, an external RESET pulse is required.

It should be noted that, if the Watchdog function is

enabled, a HALT instruction will not disable the os-

cillator. This to avoid stopping the Watchdog if a

HALT

code is executed in error. When this occurs,

the CPU will be reset when the Watchdog times

out or when an external reset is applied.

When a HALT instruction is executed, the main

crystal oscillator is stopped and any spurious

clocks are ignored. Other analog systems such as

the on-chip line PLL (for VPS/WSS) or the whole

Video chain (Slicers & Sync Extraction) must be

stopped separately by the software as they will in-

duce static consumption.

Build-up Counter

RCCU

True

RESET

RESETO

Memorized

Reset

Internal

Reset

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