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ST92195D bảng dữ liệu(PDF) 170 Page - STMicroelectronics |
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ST92195D bảng dữ liệu(HTML) 170 Page - STMicroelectronics |
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170 / 249 page  170/249 ST92195C/D - VPS & WSS SLICER VPS & WSS SLICER (Cont’d) 7.8.7 Register Description VPS STATUS REGISTER (VPSSR) R240 - Read Only/Reset by writing Register Page: 6 Reset value: 0000 0000 (00h) Bit 7 = Reserved. Bit 6 = NWDATVP: New data in all five data regis- ters. Data will be written into this register with or without bi-phase errors. The error bit for each byte of data should be checked to validate any data. Reset by writing to this register or by the leading edge of VPS Window. This flag will only be set when the number of bits saved is correct for the time expected for those bits. Bit 5 = VFRMVPS: Valid Framing code for VPS. This bit is set when the framing code is error free. Reset by the leading edge of VPS window. Bit 4 = ERB5: Error in Byte for VPSD4R Data was written but a bi-phase error was detect- ed. Set by hardware when there is an error. The user must reset it by software. Bit 3 = ERB4: Error in Byte for VPSD3R Data was written but a bi-phase error was detect- ed. Set by hardware when there is an error. The user must reset it by software. Bit 2= ERB3: Error in Byte for VPSD2R Data was written but a bi-phase error was detect- ed. Set by hardware when there is an error. The user must reset it by software. Bit 1 = ERB2: Error in Byte for VPSD1R (R/W) Data was written but a bi-phase error was detect- ed. Set by hardware when there is an error. The user must reset it by software. Bit 0 = ERB1: Error in Byte for VPSD0R (R/W) Data was written but a bi-phase error was detect- ed. Set by hardware when there is an error. The user must reset it by software VPS DATA REGISTER 0 (VPSD0R) R241 - Read Only Register Page: 6 Reset value: 0000 0000 (00h) Bit 7:6 = SD[1:0]: Sound Bits. Bit 5:4 = RR[1:0]: R-Rating bits for flag to show the material may not be suitable for children. Bit 3:0 = RX[3:0]: Reserved bits for future sound applications. Presently not defined. VPS DATA REGISTER 1 (VPSD1R) R242 - Read Only Register Page: 6 Reset value: 0000 0000 (00h) Bit 7:6 = ID[1:0]: Identification of the address for this VPS line. Bit 5:1 = ADT[4:0]: Announced day of transmis- sion. Bit 0 = AMT3: Announced month of transmission. VPS DATA REGISTER 2 (VPSD2R) R243 - Read Only Register Page: 6 Reset value: 0000 0000 (00h) b7:5 = AMT[2:0]: Announced month of transmis- sion. Bit 4:0 = ASH[4:0]: Announced start of item, HOUR. 70 - NWDA TVP VFRM VPS ERB5 ERB4 ERB3 ERB2 ERB1 70 SD1 SD0 RR1 RR0 RX3 RX2 RX1 RX0 70 ID1 ID0 ADT4 ADT3 ADT2 ADT1 ADT0 AMT3 70 AMT2 AMT1 AMT0 ASH4 ASH3 ASH2 ASH1 ASH0 |
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