ST92195D datasheet(116/249 Pages) STMICROELECTRONICS

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ST92195C/D - ON SCREEN DISPLAY (OSD)

ON SCREEN DISPLAY (Cont’d)

7.4.6.2 Building a Parallel Mode, 40-Char, Full

Page Display

Page Location

The pair of adjacent 1 Kbyte blocks of page con-

tent is stored in the TDSRAM location pointed to

by the PG3..PG0 bits. The first block contains the

characters, the second block contains the attribute

bytes.

Header & Status Rows Location

The 0.5 Kbyte block containing the Header, Status

Row 0 and Status Row 1 is pointed to by the

HS3..HS0 bits. The Header/Status attributes are

stored in this block at offset 80h.

Row Scrolling Buffer Location

The scrolling buffer corresponds to the 40 bytes

following Row 23 when the scrolling feature is

used.

Figure 71. Parallel Mode (40 Characters) - Page Mapping

Figure 72. Parallel Mode (40 Characters) - Header and Status Mapping

1K TDSRAM

Row 1 Char.

Row 23 Char.

Scrolling Buffer

Free Space

Resolution 2K bytes

Block

Number

(2K)

TDSRAM

Address (hex)

Char.

TDSRAM

Address (hex)

Attr.

TDPR

Value (hex)

PG3..PG0

8000

8400

8800

8C00

9000

9400

9800

9C00

1K TDSRAM

Row 1 Attr.

Row 23 Attr.

Scrolling Buffer

Free Space

Block

Number (0.5K)

TDSRAM

Address (hex)

TDPR

Value (hex)

HS3..HS0

8000

8200

8400

8600

8800

8A00

8C00

8E00

9000

9200

9400

9600

9800

9A00

9C00

0.5K TDSRAM

Header Char.

Resolution 0.5K bytes

Status Row 0 Char.

Status Row 1 Char.

Free Space

Header Attr.

Status Row 0 Attr.

Status Row 1 Attr.

Free Space

80h

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