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MAX7313 bảng dữ liệu(PDF) 12 Page - Maxim Integrated Products |
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MAX7313 bảng dữ liệu(HTML) 12 Page - Maxim Integrated Products |
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12 / 27 page ![]() Command Address Autoincrementing The command address stored in the MAX7313 circu- lates around grouped register functions after each data byte is written or read (Table 2). Device Reset If a device reset input is needed, consider the MAX7314. The MAX7314 includes a RST input, which clears any transaction to or from the MAX7314 on the serial interface and configures the internal registers to the same state as a power-up reset. Detailed Description Initial Power-Up On power-up all control registers are reset and the MAX7313 enters standby mode (Table 3). Power-up status makes all ports into inputs and disables both the PWM oscillator and blink functionality. Configuration Register The configuration register is used to configure the PWM intensity mode, interrupt, and blink behavior, operate the INT/O16 output, and read back the interrupt status (Table 4). 16-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion Protection 12 ______________________________________________________________________________________ Figure 10. Read, Write, and Interrupt Timing Diagrams SLAVE ADDRESS 1 2 3 4567 89 S A6 A5 A4 A3 A2 A1 A00 A 0 0 0 00 00 COMMAND BYTE 1A A A P START CONDITION ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE STOP CONDITION P7–P0 P15– P8 DATA1 VALID DATA2 VALID SLAVE ADDRESS 1 2 3 4567 89 S A6A5A4A3A2A1A0 1 A COMMAND BYTE ANA START CONDITION ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM MASTER P7–P0 P15–P8 STOP CONDITION P NO ACKNOWLEDGE FROM MASTER DATA2 DATA4 DATA3 tDV tDV SLAVE ADDRESS 1 2 3 4567 89 S A6A5A4A3A2A1A0 1 A COMMAND BYTE ANA START CONDITION ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM MASTER P7–P0 P15–P8 STOP CONDITION P NO ACKNOWLEDGE FROM MASTER DATA1 DATA2 DATA3 DATA4 DATA6 DATA5 tDH tDS DATA1 tIV tIR tIR tIV SCL SDA SCL SDA SCL SDA WRITE TO OUTPUT PORTS REGISTERS (BLINK PHASE 0 REGISTERS/BLINK PHASE 1 REGISTERS) READ FROM INPUT PORTS REGISTERS INTERRUPT VALID/RESET R/W MSB LSB DATA1 MSB LSB DATA1 MSB LSB DATA2 MSB LSB DATA4 MSB LSB DATA6 MSB LSB DATA2 R/W R/W INT |
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