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CS42436 bảng dữ liệu(PDF) 34 Page - Cirrus Logic

tên linh kiện CS42436
Giải thích chi tiết về linh kiện  108 dB, 192 kHz 6-in, 6-out TDM CODEC
PDF  66 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS42436 bảng dữ liệu(HTML) 34 Page - Cirrus Logic

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34
DS647PP2
De-emphasis is only available in Single Speed Mode. Please see “DAC De-Emphasis Control
(DAC_DEM)” on page 46 for de-emphasis control.
5.4
System Clocking
The CODEC serial audio interface ports operate as a slave and accept externally generated clocks.
The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must
be an integer multiple of, and synchronous with, the system sample rate, Fs.
Hardware Mode
The allowable ratios include 256Fs and 512Fs in Single-Speed Mode and 256Fs in Double-Speed Mode.
The frequency of MCLK must be specified using the MFREQ (pin 3). See Table 5 below for the required
frequency range.
Software Mode
The frequency range of MCLK must be specified using the MFREQ bits in register “MCLK Frequency
(MFreq[2:0])” on page 45.
5.5
CODEC Digital Interface
The ADC and DAC serial ports operate as a slave and support the TDM digital interface formats with vary-
ing bit depths from 16 to 32 as shown in Figure 14. Data is clocked out of the ADC on the falling edge of
SCLK and clocked into the DAC on the rising edge.
TDM is the only interface supported in hardware and software mode.
5.5.1 TDM
Data is received most significant bit (MSB) first, on the second rising edge of the SCLK occurring
after an FS rising edge. All data is valid on the rising edge of SCLK. The AIN1 MSB is transmitted
early but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted
on the falling edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left justified
within the time slot. Valid data lengths are 16, 18, 20, or 24.
SCLK must operate at 256Fs. FS identifies the start of a new frame and is equal to the sample
rate, Fs.
Ratio (xFs)
MFREQ
Description
SSM
DSM
QSM
0
1.5360 MHz to 12.8000 MHz
256
N/A
N/A
1
2.0480 MHz to 25.6000 MHz
512
256
N/A
Table 5. MCLK Frequency Settings
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1
F2
3.183 kHz
10.61 kHz
Figure 13. De-Emphasis Curve



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