CS42418 datasheet(63/67 Pages) CIRRUS

63 / 67 page

CS42418

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(For CQ, TA = -10 to +70° C; For DQ, TA = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;

Inputs: Logic 0 = DGND, Logic 1 = VLC, CL =30pF)

Notes: 19. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is

dictated by the timing requirements necessary to access the Channel Status and User Bit buffer

memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum

allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should

be safe for all possible conditions.

20. Data must be held for sufficient time to bridge the transition time of CCLK.

21. For fsck <1 MHz.

Parameter

Symbol

Min

Typ

Max

Units

CCLK Clock Frequency

(Note 19)

fsck

6.0

MHz

CS High Time Between Transmissions

tcsh

1.0

µs

CS Falling to CCLK Edge

tcss

CCLK Low Time

tscl

CCLK High Time

tsch

CDIN to CCLK Rising Setup Time

tdsu

CCLK Rising to DATA Hold Time

(Note 20)

tdh

CCLK Falling to CDOUT Stable

tpd

Rise Time of CDOUT

tr1

Fall Time of CDOUT

tf1

Rise Time of CCLK and CDIN

(Note 21)

tr2

100

Fall Time of CCLK and CDIN

(Note 21)

tf2

100

t r2

t f2

t dsu

t dh

t sch

t scl

CCLK

CDIN

t css

t pd

CDOUT

t csh

Figure 59. Control Port Timing - SPI Format

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