CS8920A datasheet(4/144 Pages) CIRRUS

4 / 144 page

1.0

INTRODUCTION

1.1

General Description

The CS8920A is a single-chip, ISA Plug-and-

Pl ay,

fu ll-dupl ex,

Ethernet

soluti on,

incorporating all of the analog and digital cir-

c uit ry ne ede d for a compl ete Eth erne t

circuit. Major functional blocks include: indus-

try-standard plug-and-play protocol engine, a

direct ISA-bus interface, an 802.3 MAC engine

with auto-negotiation and wake-up frame recog-

nition capability, integrated buffer memory; a

serial EEPROM interface, and a complete analog

front end with both 10BASE-T and AUI.

Plug and Play

The CS8920A implements Plug and Play in ac-

cordance with the Intel/Microsoft Plug and Play

ISA Specification Version 1.0a, allowing inter-

rupts, DMA channels, IO base address, memory

base address, and optional BootPROM address

to be selected dynamically, by either a system

BIOS, an operating system or an application pro-

gram such as the Configuration Manager. The

CS8920A supports 11 interrupts and 3 DMA

channels.

Direct ISA-Bus Interface

The CS8920A has a direct ISA-bus interface

with full 24 mA drive capability. The CS8920A

operates in either 24-bit memory space, 16-bit

I/O space, or with external DMA controllers

(three 16-bit channels), providing maximum de-

sign flexibility.

Integrated Memory

The CS8920A incorporates a 4-Kbyte page of

on-chip memory, eliminating the cost and board

area associated with external memory chips. Un-

like most other Ethernet controllers, the

CS8920A buffers entire transmit and receive

frames on chip, eliminating the need for com-

plex, inefficient memory management schemes.

The on-chip buffer manager supports full-duplex

operation.

802.3 Ethernet MAC Engine

The CS8920A’s Ethernet Media Access Control

(MAC) engine is fully compliant with the IEEE

802.3 Ethernet standard (ISO/IEC 8802-3, 1993),

and supports full-duplex operation. The full-du-

plex mode may be entered by a command from

the host, or via auto-negotiation using link-pulse

signaling.

Magic Packet Frames

The MAC machine recognizes Magic Packet

frames, and can send a wakeup signal to a sys-

tem power management chip via a dedicated

control line or via an interrupt pin.

EEPROM Interface

Th e C S89 20A prov ide s a simpl e seri al

EEPROM interface that allows configuration in-

formation to be stored in EEPROM, and then

loaded automatically at power-up.

Complete Analog Front End

The CS8920A’s analog front end incorporates a

Manchester encoder/decoder, clock recovery cir-

cuit, 10BASE-T transceiver, and complete

Attachment Unit Interface (AUI). It provides

manual and automatic selection of either

10BASE-T or AUI, and offers three on-chip

LED drivers for link status, bus status, and Eth-

ernet line activity.

The 10BASE-T transceiver includes drivers, re-

ceivers, and analog filters, allowing direct

connection to low-cost isolation transformers. It

supports 100, 120, and

150 Ω shielded and un-

shielded cables, extended cable lengths.

CS8920A

DS238PP1

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