CS5504 datasheet(7/24 Pages) CIRRUS

7 / 24 page

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;

VA- = -5V

± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter

Symbol

Min

Typ

Max

Units

Serial Clock

fsclk

2.5

MHz

Serial Clock

Pulse Width High

Pulse Width Low

tph

tpl

200

Access Time:

CS Low to data valid (Note 15)

tcsd

200

Maximum Delay Time:

(Note 16)

SCLK falling to new SDATA bit

tdd

150

310

Output Float Delay:

CS high to output Hi-Z (Note 17)

SCLK falling to Hi-Z

tfd1

tfd2

160

150

300

Notes: 15. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high

for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To

guarantee proper clocking of SDATA when using asynchronous CS, SCLK should not be taken high

sooner than 2/fclk + 200 ns after CS goes low.

16. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the

serial port shifting mechanism before falling edges can be recognized.

17. If CS is returned high before all data bits are output, the SDATA output will complete the current data

bit and then go to high impedance.

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VD+ = 3.3V ±

5%; VA- = -5V

± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter

Symbol

Min

Typ

Max

Units

Serial Clock

fsclk

1.25

MHz

Serial Clock

Pulse Width High

Pulse Width Low

tph

tpl

200

Access Time:

CS Low to data valid (Note 15)

tcsd

100

200

Maximum Delay Time:

(Note 16)

SCLK falling to new SDATA bit

tdd

400

600

Output Float Delay:

CS high to output Hi-Z (Note 17)

SCLK falling to Hi-Z

tfd1

tfd2

320

150

500

CS5504

DS126F1

CS5504

DS126F2

CS5504 bảng dữ liệu(PDF) 7 Page - Cirrus Logic

CS5504 bảng dữ liệu(HTML) 7 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

bảng dữ liệu tải về

Link URL