DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Preliminary
35
Version: DM9601-DS-P01
June 22, 2001
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
16.6
RESERVED
0, RO
Reserved
Write as 0, ignore on read
16.5
RESERVED
0, RO
Reserved
Write as 0, ignore on read
16.4
RPDCTR-EN
1, RW
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 : Disable automatic reduced power down
1 : Enable automatic reduced power down
16.3
SMRST
0, RW
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
16.2
MFPSC
0, RW
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
16.1
SLEEP
0, RW
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
16.0
RLOUT
0, RW
Remote Loopout Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
11.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
Bit Name
Default
Description
17.15
100FDX
1, RO
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M full duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
17.14
100HDX
1, RO
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M half duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
17.13
10FDX
1, RO
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M Full Duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode.
17.12
10HDX
1, RO
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
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