P89C60X2BASLASH00 datasheet(46/56 Pages) PHILIPS

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Philips Semiconductors

Product data

P89C60X2/61X2

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

2003 Sep 11

DC ELECTRICAL CHARACTERISTICS

Tamb = 0 °C to +70 °C; VCC = 5 V ±10%; VSS = 0 V (20/33 MHz max. CPU clock)

SYMBOL

PARAMETER

TEST

CONDITIONS

LIMITS

UNIT

MIN

TYP1

MAX

VIL

Input low voltage11

4.5 V < VCC < 5.5 V

–0.5

0.2 VCC–0.1

VIH

Input high voltage (ports 0, 1, 2, 3, EA)

–

0.2 VCC+0.9

VCC+0.5

VIH1

Input high voltage, XTAL1, RST11

–

0.7 VCC

VCC+0.5

VOL

Output low voltage, ports 1, 2, 3 8

VCC = 4.5 V; IOL = 1.6 mA2

–

0.4

VOL1

Output low voltage, port 0, ALE, PSEN 7, 8

VCC = 4.5 V; IOL = 3.2 mA2

–

0.45

VOH

Output high voltage, ports 1, 2, 3 3

VCC = 4.5 V; IOH = –30 mA

VCC – 0.7

–

VOH1

Output high voltage (port 0 in external bus

mode), ALE9, PSEN3

VCC = 4.5 V; IOH = –3.2 mA VCC – 0.7

–

IIL

Logical 0 input current, ports 1, 2, 3

VIN = 0.4 V

–1

–75

ITL

Logical 1-to-0 transition current, ports 1, 2, 36

VIN = 2.0 V; See note 4

–

–650

ILI

Input leakage current, port 0

0.45 < VIN < VCC – 0.3

–

±10

ICC

Power supply current (see Figure 38):

See note 5

Active mode (see Note 5)

Idle mode (see Note 5)

Power-down mode or clock stopped

Tamb = 0 °C to 70 °C

<30

100

(see Figure 42 for conditions)

Programming and erase mode

fOSC = 20MHz

RRST

Internal reset pull-down resistor

–

225

Ω

CIO

Pin capacitance10 (except EA)

–

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no

single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when VIN is approximately 2 V.

5. See Figures 39 through 42 for ICC test conditions and Figure 38 for ICC vs. Frequency.

12-clock mode characteristics:

Active mode:

ICC (MAX) = (8.5 + 0.62 FREQ. [MHz])mA

Idle mode:

ICC (MAX) = (3.5 + 0.18 FREQ. [MHz])mA

6. This value applies to Tamb = 0°C to +70°C.

7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin:

15 mA

Maximum IOL per 8-bit port:

26 mA

Maximum total IOL for all outputs:

71 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

test conditions.

9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.

10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF

(except EA is 25 pF).

11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection

circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.

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