WM8771

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PP Rev 2.0 December 2001

10

DIGITAL AUDIO INTERFACE – SLAVE MODE

BCLK

DOUT

ADCLRC

DIN1/2/3/4

DACLRC

WM8771

CODEC

DSP

ENCODER/

DECODER

4

Figure 4 Audio Interface – Slave Mode

BCLK

DACLRC/

ADCLRC

t

BCH

t

BCL

t

BCY

DIN1/2/3/4

DOUT

t

LRSU

t

DS

t

LRH

t

DH

t

DD

Figure 5 Digital Audio Data Timing – Slave Mode

Test Conditions

stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

50

ns

BCLK pulse width high

20

ns

BCLK pulse width low

20

ns

DACLRC/ADCLRC set-up

time to BCLK rising edge

10

ns

DACLRC/ADCLRC hold

time from BCLK rising edge

10

ns

DIN1/2/3/4 set-up time to

BCLK rising edge

10

ns

DIN1/2/3/4 hold time from

BCLK rising edge

10

ns

DOUT propagation delay

from BCLK falling edge

0

10

ns

Table 3 Digital Audio Data Timing – Slave Mode

Note: ADCLRC and DACLRC should be synchronous with MCLK, although the WM8771 interface is tolerant of phase variations or jitter on these signals.